Searched refs:RISCVAsmParser (Results 1 – 4 of 4) sorted by relevance
45 class RISCVAsmParser : public MCTargetAsmParser { class150 RISCVAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, in RISCVAsmParser() function in __anond849e6730111::RISCVAsmParser268 return RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm) && in isBareSymbol()736 bool RISCVAsmParser::generateImmOutOfRangeError( in generateImmOutOfRangeError()958 RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) { in parseCSRSystemRegister()1124 RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) { in parseMemOpBaseReg()1231 bool RISCVAsmParser::classifySymbolRef(const MCExpr *Expr, in classifySymbolRef()1276 bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) { in ParseDirective()1289 bool RISCVAsmParser::parseDirectiveOption() { in parseDirectiveOption()1476 RegisterMCAsmParser<RISCVAsmParser> X(getTheRISCV32Target()); in LLVMInitializeRISCVAsmParser()[all …]
92 def RISCVAsmParser : AsmParser {103 let AssemblyParsers = [RISCVAsmParser];
26 // 32-bit sub-register, RISCVAsmParser will need to coerce a register number
1133 SRCS_MIN+= Target/RISCV/AsmParser/RISCVAsmParser.cpp