Home
last modified time | relevance | path

Searched refs:ProcResource (Results 1 – 25 of 39) sorted by relevance

12

/freebsd-12.1/contrib/llvm/tools/llvm-mca/Views/
H A DResourcePressureView.cpp30 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in ResourcePressureView() local
31 unsigned NumUnits = ProcResource.NumUnits; in ResourcePressureView()
33 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in ResourcePressureView()
37 R2VIndex += ProcResource.NumUnits; in ResourcePressureView()
73 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printColumnNames() local
74 unsigned NumUnits = ProcResource.NumUnits; in printColumnNames()
76 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printColumnNames()
112 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printResourcePressurePerIter() local
113 unsigned NumUnits = ProcResource.NumUnits; in printResourcePressurePerIter()
115 if (ProcResource.SubUnitsIdxBegin || !NumUnits) in printResourcePressurePerIter()
[all …]
H A DSchedulerStatistics.cpp146 const MCProcResourceDesc &ProcResource = *SM.getProcResource(I); in printSchedulerUsage() local
147 if (ProcResource.BufferSize <= 0) in printSchedulerUsage()
152 double AlmostFullThreshold = (double)(ProcResource.BufferSize * 4) / 5; in printSchedulerUsage()
156 FOS << ProcResource.Name; in printSchedulerUsage()
165 BU.MaxUsedSlots == static_cast<unsigned>(ProcResource.BufferSize)) in printSchedulerUsage()
171 FOS << ProcResource.BufferSize << '\n'; in printSchedulerUsage()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td38 def FalkorUnitB : ProcResource<1>; // Branch
39 def FalkorUnitLD : ProcResource<1>; // Load pipe
40 def FalkorUnitSD : ProcResource<1>; // Store data
41 def FalkorUnitST : ProcResource<1>; // Store pipe
43 def FalkorUnitY : ProcResource<1>; // Simple arithmetic
44 def FalkorUnitZ : ProcResource<1>; // Simple arithmetic
46 def FalkorUnitVSD : ProcResource<1>; // Vector store data
47 def FalkorUnitVX : ProcResource<1>; // Vector X-pipe
48 def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe
50 def FalkorUnitGTOV : ProcResource<1>; // Scalar to Vector
[all …]
H A DAArch64SchedExynosM4.td36 def M4UnitA : ProcResource<2>; // Simple integer
42 def M4UnitB : ProcResource<2>; // Branch
43 def M4UnitL0 : ProcResource<1>; // Load
44 def M4UnitS0 : ProcResource<1>; // Store
45 def M4PipeLS : ProcResource<1>; // Load/Store
47 def M4UnitL1 : ProcResource<1>;
48 def M4UnitS1 : ProcResource<1>;
50 def M4PipeF0 : ProcResource<1>; // FP #0
63 def M4PipeF1 : ProcResource<1>; // FP #1
69 def M4UnitFST0 : ProcResource<1>; // FP store
[all …]
H A DAArch64SchedExynosM3.td37 def M3UnitA : ProcResource<2>; // Simple integer
40 def M3UnitB : ProcResource<2>; // Branch
41 def M3UnitL : ProcResource<2>; // Load
42 def M3UnitS : ProcResource<1>; // Store
43 def M3PipeF0 : ProcResource<1>; // FP #0
46 def M3UnitFADD0 : ProcResource<1>; // Simple FP
54 def M3PipeF1 : ProcResource<1>; // FP #1
57 def M3UnitFADD1 : ProcResource<1>; // Simple FP
60 def M3UnitFST0 : ProcResource<1>; // FP store
67 def M3PipeF2 : ProcResource<1>; // FP #2
[all …]
H A DAArch64SchedKryo.td41 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops
42 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops
43 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops
44 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops
53 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops
54 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops
H A DAArch64SchedExynosM1.td37 def M1UnitA : ProcResource<2>; // Simple integer
40 def M1UnitB : ProcResource<2>; // Branch
41 def M1UnitL : ProcResource<1>; // Load
42 def M1UnitS : ProcResource<1>; // Store
43 def M1PipeF0 : ProcResource<1>; // FP #0
46 def M1UnitNAL0 : ProcResource<1>; // Simple vector
47 def M1UnitNMISC : ProcResource<1>; // Miscellanea
51 def M1PipeF1 : ProcResource<1>; // FP #1
53 def M1UnitFADD : ProcResource<1>; // Simple FP
54 def M1UnitNAL1 : ProcResource<1>; // Simple vector
[all …]
H A DAArch64SchedA53.td37 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
40 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
41 def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
42 def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
43 def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
44 def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
45 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
46 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
H A DAArch64SchedThunderX.td36 def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
37 def THXT8XUnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
38 def THXT8XUnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
39 def THXT8XUnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
40 def THXT8XUnitBr : ProcResource<1> { let BufferSize = 0; } // Branch
41 def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
42 def THXT8XUnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt
H A DAArch64SchedCyclone.td29 def CyUnitI : ProcResource<4> {
34 def CyUnitB : ProcResource<2> {
40 def CyUnitBR : ProcResource<1> {
46 def CyUnitIS : ProcResource<2> {
52 def CyUnitIM : ProcResource<1> {
58 def CyUnitID : ProcResource<1> {
68 def CyUnitLS : ProcResource<2> {
73 def CyUnitV : ProcResource<3> {
77 def CyUnitVM : ProcResource<2> {
82 def CyUnitVD : ProcResource<1> {
[all …]
H A DAArch64SchedA57.td43 def A57UnitB : ProcResource<1>; // Type B micro-ops
44 def A57UnitI : ProcResource<2>; // Type I micro-ops
45 def A57UnitM : ProcResource<1>; // Type M micro-ops
46 def A57UnitL : ProcResource<1>; // Type L micro-ops
47 def A57UnitS : ProcResource<1>; // Type S micro-ops
48 def A57UnitX : ProcResource<1>; // Type X micro-ops
49 def A57UnitW : ProcResource<1>; // Type W micro-ops
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td77 def ALU : ProcResource<4>;
78 def ALUE : ProcResource<2> {
88 def DIV : ProcResource<2>;
91 def DP : ProcResource<4>;
92 def DPE : ProcResource<2> {
96 def DPO : ProcResource<2> {
102 def LS : ProcResource<4>;
105 def PM : ProcResource<2>;
108 def DFU : ProcResource<1>;
111 def BR : ProcResource<1> {
[all …]
/freebsd-12.1/contrib/llvm/lib/MCA/Stages/
H A DInstructionTables.cpp35 const MCProcResourceDesc &ProcResource = *SM.getProcResource(Index); in execute() local
36 unsigned NumUnits = ProcResource.NumUnits; in execute()
37 if (!ProcResource.SubUnitsIdxBegin) { in execute()
51 unsigned SubUnitIdx = ProcResource.SubUnitsIdxBegin[I1]; in execute()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSISchedule.td67 def HWBranch : ProcResource<1> {
70 def HWExport : ProcResource<1> {
73 def HWLGKM : ProcResource<1> {
76 def HWSALU : ProcResource<1> {
79 def HWVMEM : ProcResource<1> {
82 def HWVALU : ProcResource<1> {
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetPfmCounters.td20 // Issue counters can be tied to a ProcResource
23 // The name of the ProcResource on which uops are issued. This is used by
26 // ProcResource.
H A DTargetSchedule.td200 class ProcResource<int num> : ProcResourceKind,
203 class ProcResGroup<list<ProcResource> resources> : ProcResourceKind {
204 list<ProcResource> Resources = resources;
283 // ProcResource item at the same position in its list. ResourceCycles
567 class MemoryQueue<ProcResource PR> {
568 ProcResource QueueDescriptor = PR;
572 class LoadQueue<ProcResource LDQueue> : MemoryQueue<LDQueue>;
573 class StoreQueue<ProcResource STQueue> : MemoryQueue<STQueue>;
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ScheduleBdVer2.td51 def PdEX0 : ProcResource<1>; // ALU, Integer Pipe0
64 def PdFPU0 : ProcResource<1>; // Vector/FPU Pipe0
65 def PdFPU1 : ProcResource<1>; // Vector/FPU Pipe1
66 def PdFPU2 : ProcResource<1>; // Vector/FPU Pipe2
67 def PdFPU3 : ProcResource<1>; // Vector/FPU Pipe3
134 def PdLoad : ProcResource<2> {
142 def PdStore : ProcResource<1> {
167 def PdFPMMA : ProcResource<1>; // PdFPU0
170 def PdFPCVT : ProcResource<1>; // PdFPU0
173 def PdFPXBR : ProcResource<1>; // PdFPU1
[all …]
H A DX86ScheduleBtVer2.td36 def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
38 def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
39 def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
89 def JDiv : ProcResource<1>; // integer division
90 def JMul : ProcResource<1>; // integer multiplication
91 def JVALU0 : ProcResource<1>; // vector integer
92 def JVALU1 : ProcResource<1>; // vector integer
93 def JVIMUL : ProcResource<1>; // vector integer multiplication
94 def JSTC : ProcResource<1>; // vector store/convert
95 def JFPM : ProcResource<1>; // FP multiplication
[all …]
H A DX86ScheduleSLM.td35 def SLM_IEC_RSV0 : ProcResource<1>;
36 def SLM_IEC_RSV1 : ProcResource<1>;
37 def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
38 def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
39 def SLM_MEC_RSV : ProcResource<1>;
45 def SLMDivider : ProcResource<1>;
46 def SLMFPMultiplier : ProcResource<1>;
47 def SLMFPDivider : ProcResource<1>;
H A DX86ScheduleZnver1.td42 def ZnALU0 : ProcResource<1>;
43 def ZnALU1 : ProcResource<1>;
44 def ZnALU2 : ProcResource<1>;
45 def ZnALU3 : ProcResource<1>;
48 def ZnAGU0 : ProcResource<1>;
49 def ZnAGU1 : ProcResource<1>;
52 def ZnFPU0 : ProcResource<1>;
53 def ZnFPU1 : ProcResource<1>;
54 def ZnFPU2 : ProcResource<1>;
55 def ZnFPU3 : ProcResource<1>;
[all …]
H A DX86SchedBroadwell.td41 def BWPort0 : ProcResource<1>;
42 def BWPort1 : ProcResource<1>;
43 def BWPort2 : ProcResource<1>;
44 def BWPort3 : ProcResource<1>;
45 def BWPort4 : ProcResource<1>;
46 def BWPort5 : ProcResource<1>;
47 def BWPort6 : ProcResource<1>;
48 def BWPort7 : ProcResource<1>;
71 def BWDivider : ProcResource<1>;
73 def BWFPDivider : ProcResource<1>;
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td30 def P5600ALQ : ProcResource<1> { let BufferSize = 16; }
31 def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; }
45 def P5600AGQ : ProcResource<3> { let BufferSize = 16; }
46 def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; }
47 def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; }
48 def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; }
50 def P5600AL2Div : ProcResource<1>;
52 def P5600CTISTD : ProcResource<1>;
218 def P5600FPQ : ProcResource<3> { let BufferSize = 16; }
219 def P5600IssueFPUS : ProcResource<1> { let Super = P5600FPQ; }
[all …]
H A DMipsScheduleGeneric.td40 def GenericALU : ProcResource<1> { let BufferSize = 1; }
41 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
59 def GenericMDU : ProcResource<1> { let BufferSize = 1; }
60 def GenericIssueMDU : ProcResource<1> { let Super = GenericALU; }
61 def GenericIssueDIV : ProcResource<1> { let Super = GenericMDU; }
148 def GenericLDST : ProcResource<1> { let BufferSize = 1; }
149 def GenericIssueLDST : ProcResource<1> { let Super = GenericLDST; }
187 def GenericCOP0 : ProcResource<1> { let BufferSize = 1; }
224 def GenericCOP2 : ProcResource<1> { let BufferSize = 1; }
348 def GenericFPQ : ProcResource<1> { let BufferSize = 1; }
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td55 def ALU : ProcResource<1> { let BufferSize = 0; }
56 def LdSt : ProcResource<1> { let BufferSize = 0; }
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMScheduleR52.td34 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
37 def R52UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
38 def R52UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
39 def R52UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
40 def R52UnitLd : ProcResource<1> { let BufferSize = 0; } // Load/Store
41 def R52UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
42 def R52UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU
43 def R52UnitFPMUL : ProcResource<2> { let BufferSize = 0; } // FP MUL
44 def R52UnitFPDIV : ProcResource<1> { let BufferSize = 0; } // FP DIV

12