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Searched refs:PredEdge (Results 1 – 6 of 6) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DGCNILPSched.cpp277 for (const auto &PredEdge : SU->Preds) { in releasePredecessors() local
278 auto PredSU = PredEdge.getSUnit(); in releasePredecessors()
279 if (PredEdge.isWeak()) in releasePredecessors()
283 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge.getLatency()); in releasePredecessors()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp100 void ReleasePred(SUnit *SU, SDep *PredEdge);
140 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { in ReleasePred() argument
141 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
H A DScheduleDAGRRList.cpp245 void ReleasePred(SUnit *SU, const SDep *PredEdge);
252 void CapturePred(SDep *PredEdge);
393 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred() argument
394 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
409 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency()); in ReleasePred()
814 void ScheduleDAGRRList::CapturePred(SDep *PredEdge) { in CapturePred() argument
815 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DMachineScheduler.cpp666 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { in releasePred() argument
667 SUnit *PredSU = PredEdge->getSUnit(); in releasePred()
669 if (PredEdge->isWeak()) { in releasePred()
671 if (PredEdge->isCluster()) in releasePred()
685 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) in releasePred()
686 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency(); in releasePred()
H A DMachinePipeliner.cpp3524 for (SDep &PredEdge : SU->Preds) { in checkValidNodeOrder()
3525 SUnit *PredSU = PredEdge.getSUnit(); in checkValidNodeOrder()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DMachineScheduler.h390 void releasePred(SUnit *SU, SDep *PredEdge);