| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | DAGISelEmitter.cpp | 154 std::vector<const PatternToMatch*> Patterns; in run() local
157 Patterns.push_back(&*I); in run()
161 std::stable_sort(Patterns.begin(), Patterns.end(), in run()
167 for (unsigned i = 0, e = Patterns.size(); i != e; ++i) { in run()
169 if (Matcher *M = ConvertPatternToMatcher(*Patterns[i], Variant, CGP)) in run()
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| /freebsd-12.1/contrib/llvm/tools/clang/lib/ASTMatchers/ |
| H A D | ASTMatchersInternal.cpp | 408 Patterns.push_back({Name, Name.startswith("::")}); in PatternSet()
415 for (size_t I = 0; I < Patterns.size();) { in consumeNameSuffix()
421 Patterns.erase(Patterns.begin() + I); in consumeNameSuffix()
424 return !Patterns.empty(); in consumeNameSuffix()
431 for (auto& P: Patterns) in foundMatch()
443 llvm::SmallVector<Pattern, 8> Patterns; member in clang::ast_matchers::internal::__anon8b8be5530611::PatternSet
458 PatternSet Patterns(Names); in matchesNodeFullFast() local
469 if (!Patterns.consumeNameSuffix(getNodeName(Node, Scratch), in matchesNodeFullFast()
478 return Patterns.foundMatch(/*AllowFullyQualified=*/false); in matchesNodeFullFast()
481 if (Patterns.foundMatch(/*AllowFullyQualified=*/false)) in matchesNodeFullFast()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3609 Patterns.push_back(MachineCombinerPattern::MULADDW_OP1); in getMaddPatterns()
3614 Patterns.push_back(MachineCombinerPattern::MULADDW_OP2); in getMaddPatterns()
3621 Patterns.push_back(MachineCombinerPattern::MULADDX_OP1); in getMaddPatterns()
3626 Patterns.push_back(MachineCombinerPattern::MULADDX_OP2); in getMaddPatterns()
3633 Patterns.push_back(MachineCombinerPattern::MULSUBW_OP1); in getMaddPatterns()
3638 Patterns.push_back(MachineCombinerPattern::MULSUBW_OP2); in getMaddPatterns()
3645 Patterns.push_back(MachineCombinerPattern::MULSUBX_OP1); in getMaddPatterns()
3650 Patterns.push_back(MachineCombinerPattern::MULSUBX_OP2); in getMaddPatterns()
3953 SmallVectorImpl<MachineCombinerPattern> &Patterns) const { in getMachineCombinerPatterns()
3955 if (getMaddPatterns(Root, Patterns)) in getMachineCombinerPatterns()
[all …]
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| H A D | AArch64InstrInfo.h | 208 SmallVectorImpl<MachineCombinerPattern> &Patterns) const override;
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | MachineCombiner.cpp | 114 SmallVector<MachineCombinerPattern, 16> &Patterns);
464 SmallVector<MachineCombinerPattern, 16> &Patterns) { in verifyPatternOrder() argument
467 for (auto P : Patterns) { in verifyPatternOrder()
513 SmallVector<MachineCombinerPattern, 16> Patterns; in combineInstructions() local
541 if (!TII->getMachineCombinerPatterns(MI, Patterns)) in combineInstructions()
545 verifyPatternOrder(MBB, MI, Patterns); in combineInstructions()
547 for (auto P : Patterns) { in combineInstructions()
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| H A D | TargetInstrInfo.cpp | 735 SmallVectorImpl<MachineCombinerPattern> &Patterns) const { in getMachineCombinerPatterns()
743 Patterns.push_back(MachineCombinerPattern::REASSOC_AX_YB); in getMachineCombinerPatterns()
744 Patterns.push_back(MachineCombinerPattern::REASSOC_XA_YB); in getMachineCombinerPatterns()
746 Patterns.push_back(MachineCombinerPattern::REASSOC_AX_BY); in getMachineCombinerPatterns()
747 Patterns.push_back(MachineCombinerPattern::REASSOC_XA_BY); in getMachineCombinerPatterns()
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| /freebsd-12.1/contrib/llvm/tools/lld/Common/ |
| H A D | Strings.cpp | 63 Patterns.push_back(*Pat); in StringMatcher()
68 for (const GlobPattern &Pat : Patterns) in match()
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| /freebsd-12.1/contrib/llvm/tools/lld/include/lld/Common/ |
| H A D | Strings.h | 41 std::vector<llvm::GlobPattern> Patterns;
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| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrCall.td | 119 // Patterns for matching a direct call to a global address.
146 // Patterns for matching a direct call to an external symbol.
|
| H A D | WebAssemblyInstrAtomics.td | 458 // Patterns for various addressing modes.
535 // Patterns for various addressing modes for truncating-extending binary RMWs.
725 // Patterns for various addressing modes.
795 // Patterns for various addressing modes for truncating-extending ternary RMWs.
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstructions.td | 592 // VOP1 Patterns
679 // VOP2 Patterns
1055 /********** Immediate Patterns **********/
1115 /********** Intrinsic Patterns **********/
1144 // VOP3 Patterns
1195 // SAD Patterns
1214 // Conversion Patterns
1371 // Miscellaneous Patterns
1568 // Fract Patterns
1601 // Miscellaneous Optimization Patterns
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| H A D | AMDGPUGISel.td | 1 //===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===//
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| H A D | SOPInstructions.td | 1040 // SOP1 Patterns
1068 // SOP2 Patterns
1102 // SOPP Patterns
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| H A D | R600Instructions.td | 1675 // ISel Patterns
1680 // CND*_INT Patterns for f32 True / False values
1697 // KIL Patterns
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| H A D | FLATInstructions.td | 658 // Flat Patterns
661 // Patterns for global loads with no offset.
|
| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | Mips64r6InstrInfo.td | 201 // Patterns and Pseudo Instructions
302 // Patterns used for matching away redundant sign extensions.
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| H A D | MicroMipsInstrFPU.td | 399 // Floating Point Patterns
402 // Patterns for loads/stores with a reg+imm operand.
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| H A D | MipsInstrFPU.td | 893 // Floating Point Patterns
956 // Patterns for loads/stores with a reg+imm operand.
|
| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrVecCompiler.td | 1 //===- X86InstrVecCompiler.td - Vector Compiler Patterns ---*- tablegen -*-===//
57 // Patterns for insert_subvector/extract_subvector to/from index=0
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 948 SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
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| /freebsd-12.1/contrib/gcc/doc/ |
| H A D | md.texi | 43 * Including Patterns:: Including Patterns in Machine Descriptions.
101 @node Patterns
4220 @xref{Looping Patterns}.
4684 @cindex Ordering of Patterns
4706 @node Dependent Patterns
4707 @section Interdependence of Patterns
4708 @cindex Dependent Patterns
4709 @cindex Interdependence of Patterns
4788 @node Jump Patterns
4903 @node Looping Patterns
[all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 1831 // Patterns to select load-indexed: Rs + Off.
1842 // Patterns to select load-indexed: Rs + Off.
1853 // Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi.
1860 // Patterns to select load reg indexed: Rs + Off with a value modifier.
1871 // Patterns to select load reg indexed: Rs + Off with a value modifier.
1882 // Patterns to select load reg indexed: Rs + Off with a value modifier.
2164 // Patterns for loads of i1:
2185 // Patterns for generating stores, where the address takes different forms:
2216 // Patterns for generating stores, where the address takes different forms,
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| H A D | HexagonIntrinsics.td | 241 // Patterns for optimizing code generations for HVX.
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| /freebsd-12.1/contrib/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.td | 21 // Instruction Operands and Patterns
829 // Non-Instruction Patterns
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstr64Bit.td | 1275 // Patterns to match the pre-inc stores. We can't put the patterns on
1336 // Instruction Patterns
1426 // Patterns to match r+r indexed loads and stores for
|