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Searched refs:Order (Results 1 – 25 of 133) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h52 unsigned Order; variable
62 : Var(Var), Expr(Expr), DL(std::move(dl)), Order(O), IsIndirect(indir) { in SDDbgValue()
71 : Var(Var), Expr(Expr), DL(std::move(dl)), Order(O), IsIndirect(false) { in SDDbgValue()
78 bool IsIndirect, DebugLoc DL, unsigned Order, in SDDbgValue() argument
80 : Var(Var), Expr(Expr), DL(DL), Order(Order), IsIndirect(IsIndirect) { in SDDbgValue()
122 unsigned getOrder() const { return Order; } in getOrder()
147 unsigned Order; variable
151 : Label(Label), DL(std::move(dl)), Order(O) {} in SDDbgLabel()
161 unsigned getOrder() const { return Order; } in getOrder()
H A DScheduleDAGSDNodes.cpp728 if (!Order || DVOrder == Order) { in ProcessSDDbgValues()
746 unsigned Order = N->getIROrder(); in ProcessSourceNode() local
747 if (!Order || !Seen.insert(Order).second) { in ProcessSourceNode()
761 Orders.push_back({Order, (MachineInstr *)nullptr}); in ProcessSourceNode()
765 Orders.push_back({Order, &*std::prev(IP)}); in ProcessSourceNode()
766 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order); in ProcessSourceNode()
887 unsigned Order = Orders[i].first; in EmitSchedule() local
893 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
911 LastOrder = Order; in EmitSchedule()
934 unsigned Order = InstrOrder.first; in EmitSchedule() local
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/freebsd-12.1/contrib/llvm/lib/Support/
H A DDynamicLibrary.cpp77 void *LibLookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in LibLookup() argument
78 if (Order & SO_LoadOrder) { in LibLookup()
92 void *Lookup(const char *Symbol, DynamicLibrary::SearchOrdering Order) { in Lookup() argument
93 assert(!((Order & SO_LoadedFirst) && (Order & SO_LoadedLast)) && in Lookup()
96 if (!Process || (Order & SO_LoadedFirst)) { in Lookup()
97 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
106 if (Order & SO_LoadedLast) { in Lookup()
107 if (void *Ptr = LibLookup(Symbol, Order)) in Lookup()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DAllocationOrder.h32 ArrayRef<MCPhysReg> Order; variable
50 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder()
61 Limit = Order.size();
63 unsigned Reg = Order[Pos++];
80 return Order[Pos++]; in nextWithDups()
H A DRegAllocGreedy.cpp762 Order.rewind(); in tryAssign()
764 while ((PhysReg = Order.next())) in tryAssign()
767 if (!PhysReg || Order.isHint()) in tryAssign()
775 if (Order.isHint(Hint)) { in tryAssign()
808 while ((PhysReg = Order.next())) { in canReassign()
1020 for (auto PhysReg : Order.getOrder()) { in getCheapestEvicteeWeight()
1131 Order.rewind(); in tryEvict()
1152 if (Order.isHint()) in tryEvict()
1864 Order.rewind(); in calculateRegionSplitCost()
2304 Order.rewind(); in tryLocalSplit()
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H A DRegisterClassInfo.cpp98 if (!RCI.Order) in compute()
99 RCI.Order.reset(new MCPhysReg[NumRegs]); in compute()
124 RCI.Order[N++] = PhysReg; in compute()
137 RCI.Order[N++] = PhysReg; in compute()
157 dbgs() << ' ' << printReg(RCI.Order[I], TRI); in compute()
H A DAllocationOrder.cpp37 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
38 if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix)) in AllocationOrder()
52 assert(is_contained(Order, Hints[I]) && in AllocationOrder()
H A DLocalStackSlotAllocation.cpp59 unsigned Order; member in __anon0ee44d820111::FrameRef
63 MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {} in FrameRef()
66 return std::tie(LocalOffset, FrameIdx, Order) < in operator <()
67 std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order); in operator <()
302 unsigned Order = 0; in insertFrameReferenceRegisters() local
330 FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++)); in insertFrameReferenceRegisters()
H A DTargetRegisterInfo.cpp213 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); in getAllocatableSetForRC() local
214 for (unsigned i = 0; i != Order.size(); ++i) in getAllocatableSetForRC()
215 R.set(Order[i]); in getAllocatableSetForRC()
393 ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
428 if (!is_contained(Order, Phys)) in getRegAllocationHints()
H A DBreakFalseDeps.cpp145 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef() local
146 for (MCPhysReg Reg : Order) { in pickBestRegisterForUndef()
H A DAggressiveAntiDepBreaker.cpp633 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters() local
634 if (Order.empty()) { in FindSuitableFreeRegisters()
641 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
644 unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR); in FindSuitableFreeRegisters()
647 if (R == 0) R = Order.size(); in FindSuitableFreeRegisters()
649 const unsigned NewSuperReg = Order[R]; in FindSuitableFreeRegisters()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h724 void setIROrder(unsigned Order) { IROrder = Order; }
1060 IROrder(Order), debugLoc(std::move(dl)) {
1089 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1090 assert(Order >= 0 && "bad IROrder");
1375 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {}
1424 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
2049 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2140 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
2143 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {}
2232 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {}
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H A DScheduleDAG.h57 Order ///< Any other ordering dependency. enumerator
125 : Dep(S, Order), Contents(), Latency(0) { in SDep()
170 return getKind() == Order && (Contents.OrdKind == MayAliasMem in isNormalMemory()
176 return getKind() == Order && Contents.OrdKind == Barrier; in isBarrier()
188 return getKind() == Order && Contents.OrdKind == MustAliasMem; in isMustAlias()
196 return getKind() == Order && Contents.OrdKind >= Weak; in isWeak()
202 return getKind() == Order && Contents.OrdKind == Artificial; in isArtificial()
208 return getKind() == Order && Contents.OrdKind == Cluster; in isCluster()
477 case Order:
H A DRegisterClassInfo.h38 std::unique_ptr<MCPhysReg[]> Order; member
43 return makeArrayRef(Order.get(), NumRegs);
/freebsd-12.1/contrib/llvm/lib/Transforms/Scalar/
H A DStructurizeCFG.cpp191 SmallVector<RegionNode *, 8> Order; member in __anon8647049c0111::StructurizeCFG
347 if (is_contained(Order, *I)) in orderNodes()
359 Order.push_back(*LoopI); in orderNodes()
369 Order.push_back(*I); in orderNodes()
376 std::reverse(Order.begin(), Order.end()); in orderNodes()
514 for (RegionNode *RN : reverse(Order)) { in collectInfos()
754 if (!Order.empty() || !ExitUseAllowed) in needPostfix()
804 RegionNode *Node = Order.pop_back_val(); in wireFlow()
839 RegionNode *Node = Order.back(); in handleLoops()
894 while (!Order.empty()) { in createFlow()
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/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.h1413 X86StoreSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, in X86StoreSDNode() argument
1416 :MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {} in X86StoreSDNode()
1431 X86MaskedStoreSDNode(unsigned Opcode, unsigned Order, in X86MaskedStoreSDNode() argument
1434 : MemSDNode(Opcode, Order, dl, VTs, MemVT, MMO) {} in X86MaskedStoreSDNode()
1449 TruncSStoreSDNode(unsigned Order, const DebugLoc &dl, in TruncSStoreSDNode() argument
1451 : X86StoreSDNode(X86ISD::VTRUNCSTORES, Order, dl, VTs, MemVT, MMO) {} in TruncSStoreSDNode()
1461 TruncUSStoreSDNode(unsigned Order, const DebugLoc &dl, in TruncUSStoreSDNode() argument
1473 MaskedTruncSStoreSDNode(unsigned Order, in MaskedTruncSStoreSDNode() argument
1486 MaskedTruncUSStoreSDNode(unsigned Order, in MaskedTruncUSStoreSDNode() argument
1501 X86MaskedGatherScatterSDNode(unsigned Opc, unsigned Order, in X86MaskedGatherScatterSDNode() argument
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def138 ArrayRef<PartialMappingIdx> Order) {
139 if (Order.front() != FirstAlias)
141 if (Order.back() != LastAlias)
143 if (Order.front() > Order.back())
146 PartialMappingIdx Previous = Order.front();
148 for (const auto &Current : Order) {
/freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/
H A DCGOpenMPRuntime.h443 explicit OffloadEntryInfo(OffloadingEntryInfoKinds Kind, unsigned Order, in OffloadEntryInfo() argument
445 : Flags(Flags), Order(Order), Kind(Kind) {} in OffloadEntryInfo()
449 bool isValid() const { return Order != ~0u; } in isValid()
450 unsigned getOrder() const { return Order; } in getOrder()
471 unsigned Order = ~0u; variable
504 explicit OffloadEntryInfoTargetRegion(unsigned Order, in OffloadEntryInfoTargetRegion() argument
508 : OffloadEntryInfo(OffloadingEntryInfoTargetRegion, Order, Flags), in OffloadEntryInfoTargetRegion()
526 unsigned Order);
564 explicit OffloadEntryInfoDeviceGlobalVar(unsigned Order, in OffloadEntryInfoDeviceGlobalVar() argument
568 unsigned Order, llvm::Constant *Addr, CharUnits VarSize, in OffloadEntryInfoDeviceGlobalVar() argument
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H A DCGAtomic.cpp551 Load->setAtomic(Order, Scope); in EmitAtomicOp()
563 Store->setAtomic(Order, Scope); in EmitAtomicOp()
685 Order, SCID); in EmitAtomicOp()
711 Order, in EmitAtomicOp()
778 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr() local
1020 Args.add(RValue::get(Order), getContext().IntTy); in EmitAtomicExpr()
1021 Order = OrderFail; in EmitAtomicExpr()
1165 Args.add(RValue::get(Order), in EmitAtomicExpr()
1213 if (isa<llvm::ConstantInt>(Order)) { in EmitAtomicExpr()
1214 auto ord = cast<llvm::ConstantInt>(Order)->getZExtValue(); in EmitAtomicExpr()
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/freebsd-12.1/contrib/llvm/lib/Bitcode/Writer/
H A DValueEnumerator.cpp737 SmallVector<MDIndex, 64> Order; in organizeMetadata() local
738 Order.reserve(MetadataMap.size()); in organizeMetadata()
740 Order.push_back(MetadataMap.lookup(MD)); in organizeMetadata()
748 llvm::sort(Order, [this](MDIndex LHS, MDIndex RHS) { in organizeMetadata()
757 for (unsigned I = 0, E = Order.size(); I != E && !Order[I].F; ++I) { in organizeMetadata()
758 auto *MD = Order[I].get(OldMDs); in organizeMetadata()
766 if (MDs.size() == Order.size()) in organizeMetadata()
773 for (unsigned I = MDs.size(), E = Order.size(), ID = MDs.size(); I != E; in organizeMetadata()
775 unsigned F = Order[I].F; in organizeMetadata()
787 auto *MD = Order[I].get(OldMDs); in organizeMetadata()
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DCodeGenRegisters.h507 unsigned Order = 0; // Cache the sort key. member
721 unsigned getRegSetIDAt(unsigned Order) const { in getRegSetIDAt() argument
722 return RegUnitSetOrder[Order]; in getRegSetIDAt()
725 const RegUnitSet &getRegSetAt(unsigned Order) const { in getRegSetAt() argument
726 return RegUnitSets[RegUnitSetOrder[Order]]; in getRegSetAt()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp59 ArrayRef<MCPhysReg> Order, in getRegAllocationHints() argument
68 VirtReg, Order, Hints, MF, VRM, Matrix); in getRegAllocationHints()
96 for (MCPhysReg Reg : Order) in getRegAllocationHints()
100 for (MCPhysReg Reg : Order) in getRegAllocationHints()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp107 Coloring(ArrayRef<Node> Ord) : Order(Ord) { in Coloring()
126 ArrayRef<Node> Order; member
134 Node Num = Order.size(); in conj()
167 Node I = Order[P]; in build()
170 Node PC = Order[conj(P)]; in build()
274 Node P = Order[I]; in dump()
337 unsigned S = Order.size(); in PermNetwork()
341 Table.resize(Order.size()); in PermNetwork()
347 unsigned Size = Order.size(); in getControls()
367 return Order.size(); in size()
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/freebsd-12.1/contrib/llvm/tools/lld/ELF/
H A DOutputSections.cpp142 llvm::function_ref<int(InputSectionBase *S)> Order) { in sortByOrder() argument
148 V.push_back({Order(S), S}); in sortByOrder()
165 void OutputSection::sort(llvm::function_ref<int(InputSectionBase *S)> Order) { in sort() argument
169 sortByOrder(ISD->Sections, Order); in sort()
/freebsd-12.1/contrib/file/magic/Magdir/
H A Dhp310 # Order 1: KERNEL, EXEC, FORMAT, PROC
332 # Order 2: KERNEL, FORMAT, EXEC, PROC
351 # Order 3: FORMAT, KERNEL, EXEC, PROC
373 # Order 4: EXEC, KERNEL, FORMAT, PROC
395 # Order 5: FORMAT, EXEC, KERNEL, PROC
417 # Order 6: EXEC, FORMAT, KERNEL, PROC

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