| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 126 unsigned Offset1; member
313 if (CI.Offset0 == CI.Offset1) in offsetsCanBeCombined()
321 unsigned EltOffset1 = CI.Offset1 / CI.EltSize; in offsetsCanBeCombined()
338 CI.Offset1 = EltOffset1 / 64; in offsetsCanBeCombined()
346 CI.Offset1 = EltOffset1; in offsetsCanBeCombined()
352 CI.BaseOff = std::min(CI.Offset0, CI.Offset1); in offsetsCanBeCombined()
635 CI.Offset1 &= 0xffff; in findMatchingInst()
692 unsigned NewOffset1 = CI.Offset1; in mergeRead2Pair()
793 unsigned NewOffset1 = CI.Offset1; in mergeWrite2Pair()
961 if (CI.Offset0 > CI.Offset1) { in getSubRegIdxs()
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| H A D | AMDGPUISelDAGToDAG.cpp | 119 SDValue &Offset1) const;
915 SDValue &Offset1) const { in SelectDS64Bit4ByteAligned()
928 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
957 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
974 Offset1 = CurDAG->getTargetConstant(DWordOffset1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
983 Offset1 = CurDAG->getTargetConstant(1, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
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| H A D | SIInstrInfo.cpp | 153 int64_t &Offset1) const { in areLoadsFromSameBasePtr()
186 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue(); in areLoadsFromSameBasePtr()
215 Offset1 = Load1Offset->getZExtValue(); in areLoadsFromSameBasePtr()
249 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue(); in areLoadsFromSameBasePtr()
295 uint8_t Offset1 = Offset1Imm->getImm(); in getMemOperandWithOffset() local
297 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) { in getMemOperandWithOffset()
482 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear()
488 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear()
2178 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local
2181 getMemOperandWithOffset(MIb, BaseOp1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
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| H A D | SIInstrInfo.h | 173 int64_t &Offset1,
184 int64_t Offset1, unsigned NumLoads) const override;
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| H A D | SIInstrInfo.td | 732 def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
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| H A D | SIISelLowering.cpp | 5488 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) | in LowerINTRINSIC_W_CHAIN() local
5490 unsigned Offset = Offset0 | (Offset1 << 8); in LowerINTRINSIC_W_CHAIN()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 224 int64_t Offset1, Offset2; in ClusterNeighboringLoads() local
225 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || in ClusterNeighboringLoads()
226 Offset1 == Offset2) in ClusterNeighboringLoads()
230 if (O2SMap.insert(std::make_pair(Offset1, Base)).second) in ClusterNeighboringLoads()
231 Offsets.push_back(Offset1); in ClusterNeighboringLoads()
234 if (Offset2 < Offset1) in ClusterNeighboringLoads()
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| H A D | DAGCombiner.cpp | 12772 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue(); in CombineToPreIndexedLoadStore() local
12783 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1; in CombineToPreIndexedLoadStore()
12784 else CNV = CNV - Offset1; in CombineToPreIndexedLoadStore()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 292 int64_t Offset1; in apply() local
294 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1); in apply()
300 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 247 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
259 int64_t Offset1, int64_t Offset2,
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| H A D | ARMBaseInstrInfo.cpp | 1738 int64_t &Offset1, in areLoadsFromSameBasePtr() argument
1799 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue(); in areLoadsFromSameBasePtr()
1819 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
1824 assert(Offset2 > Offset1); in shouldScheduleLoadsNear()
1826 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 427 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
438 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
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| H A D | X86InstrInfo.cpp | 5656 int64_t &Offset1, int64_t &Offset2) const { in areLoadsFromSameBasePtr() argument
5836 Offset1 = Disp1->getSExtValue(); in areLoadsFromSameBasePtr()
5842 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
5844 assert(Offset2 > Offset1); in shouldScheduleLoadsNear()
5845 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MicroMipsSizeReduction.cpp | 401 int64_t Offset1, Offset2; in ConsecutiveInstr() local
402 if (!GetImm(MI1, 2, Offset1)) in ConsecutiveInstr()
410 return ((Offset1 == (Offset2 - 4)) && (ConsecutiveRegisters(Reg1, Reg2))); in ConsecutiveInstr()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1120 int64_t &Offset1, in areLoadsFromSameBasePtr() argument
1134 int64_t Offset1, int64_t Offset2, in shouldScheduleLoadsNear() argument
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 2158 int64_t Offset1, unsigned Opcode1, int FI2, in shouldClusterFI() argument
2167 if (!unscaleOffset(Opcode1, Offset1) || !unscaleOffset(Opcode2, Offset2)) in shouldClusterFI()
2169 ObjectOffset1 += Offset1; in shouldClusterFI()
2219 int64_t Offset1 = FirstLdSt.getOperand(2).getImm(); in shouldClusterMemOps() local
2220 if (isUnscaledLdSt(FirstOpc) && !scaleOffset(FirstOpc, Offset1)) in shouldClusterMemOps()
2228 if (Offset1 > 63 || Offset1 < -64) in shouldClusterMemOps()
2234 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 >= Offset2) && in shouldClusterMemOps()
2239 return shouldClusterFI(MFI, BaseOp1.getIndex(), Offset1, FirstOpc, in shouldClusterMemOps()
2243 assert((!BaseOp1.isIdenticalTo(BaseOp2) || Offset1 <= Offset2) && in shouldClusterMemOps()
2246 return Offset1 + 1 == Offset2; in shouldClusterMemOps()
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| H A D | AArch64InstrFormats.td | 9342 int Offset1, int Offset2, int Offset4, int Offset8> {
9362 !cast<DAGOperand>("GPR64pi" # Offset1)>;
9365 !cast<DAGOperand>("GPR64pi" # Offset1)>;
9385 defm : SIMDLdrAliases<NAME, asm, "8b", Count, Offset1, 64>;
9386 defm : SIMDLdrAliases<NAME, asm, "16b", Count, Offset1, 128>;
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| /freebsd-12.1/contrib/llvm/lib/Transforms/Scalar/ |
| H A D | SeparateConstOffsetFromGEP.cpp | 1294 Value *Offset1 = First->getOperand(1); in swapGEPOperand() local
1297 Second->setOperand(1, Offset1); in swapGEPOperand()
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| H A D | MemCpyOptimizer.cpp | 149 int64_t Offset1 = GetOffsetFromIndex(GEP1, Idx, VariableIdxFound, DL); in IsPointerOffset() local
153 Offset = Offset2-Offset1; in IsPointerOffset()
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| /freebsd-12.1/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | IteratorChecker.cpp | 372 SymbolRef Offset1,
2234 SymbolRef Offset1, in invalidateIteratorPositions() argument
2239 return compare(State, Pos.getOffset(), Offset1, Opc1) && in invalidateIteratorPositions()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | MachinePipeliner.cpp | 535 int64_t Offset1, Offset2; in addLoopCarriedDependences() local
536 if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, TRI) && in addLoopCarriedDependences()
539 (int)Offset1 < (int)Offset2) { in addLoopCarriedDependences()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11089 int64_t Offset1 = 0, Offset2 = 0; in isConsecutiveLSLoc() local
11090 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG); in isConsecutiveLSLoc()
11092 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes)) in isConsecutiveLSLoc()
11098 Offset1 = 0; in isConsecutiveLSLoc()
11100 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1); in isConsecutiveLSLoc()
11103 return Offset1 == (Offset2 + Dist*Bytes); in isConsecutiveLSLoc()
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