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Searched refs:NumVecs (Results 1 – 7 of 7) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1746 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
1782 if (NumVecs == 1) in SelectVLD()
1785 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
1861 if (NumVecs == 1) { in SelectVLD()
1885 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
2056 if (NumVecs != 3) { in SelectVLDSTLane()
2086 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2112 if (NumVecs == 2) { in SelectVLDSTLane()
2162 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2175 if (NumVecs != 3) { in SelectVLDDup()
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H A DARMISelLowering.cpp11599 unsigned NumVecs = 0; in CombineBaseUpdate() local
11605 NumVecs = 1; break; in CombineBaseUpdate()
11607 NumVecs = 2; break; in CombineBaseUpdate()
11609 NumVecs = 3; break; in CombineBaseUpdate()
11611 NumVecs = 4; break; in CombineBaseUpdate()
11803 unsigned NumVecs = 0; in CombineVLDDUP() local
11807 NumVecs = 2; in CombineVLDDUP()
11810 NumVecs = 3; in CombineVLDDUP()
11813 NumVecs = 4; in CombineVLDDUP()
11837 for (n = 0; n < NumVecs; ++n) in CombineVLDDUP()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1093 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1)); in SelectTable()
1204 for (unsigned i = 0; i < NumVecs; ++i) in SelectLoad()
1208 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoad()
1233 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoad()
1237 if (NumVecs == 1) in SelectPostLoad()
1240 for (unsigned i = 0; i < NumVecs; ++i) in SelectPostLoad()
1353 for (unsigned i = 0; i < NumVecs; ++i) { in SelectLoadLane()
1360 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1)); in SelectLoadLane()
1394 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0)); in SelectPostLoadLane()
1398 if (NumVecs == 1) { in SelectPostLoadLane()
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H A DAArch64ISelLowering.cpp10506 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
10511 NumVecs = 2; break; in performNEONPostLDSTCombine()
10513 NumVecs = 3; break; in performNEONPostLDSTCombine()
10515 NumVecs = 4; break; in performNEONPostLDSTCombine()
10517 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
10519 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
10521 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
10523 NumVecs = 2; break; in performNEONPostLDSTCombine()
10525 NumVecs = 3; break; in performNEONPostLDSTCombine()
10527 NumVecs = 4; break; in performNEONPostLDSTCombine()
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/freebsd-12.1/contrib/llvm/lib/Analysis/
H A DVectorUtils.cpp630 unsigned NumVecs) { in createInterleaveMask() argument
633 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
688 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
689 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
695 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
697 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
704 if (NumVecs % 2 != 0) in concatenateVectors()
705 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
708 NumVecs = ResList.size(); in concatenateVectors()
709 } while (NumVecs > 1); in concatenateVectors()
/freebsd-12.1/contrib/llvm/include/llvm/Analysis/
H A DVectorUtils.h186 unsigned NumVecs);
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp39433 unsigned NumVecs = VT.getSizeInBits() / SplitSize; in combineToExtendVectorInReg() local
39442 for (unsigned i = 0, Offset = 0; i != NumVecs; ++i, Offset += NumSubElts) { in combineToExtendVectorInReg()