Lines Matching refs:NumVecs
185 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
193 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
201 unsigned NumVecs, const uint16_t *DOpcodes,
208 unsigned NumVecs, const uint16_t *DOpcodes,
244 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1602 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1603 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1604 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1737 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement() argument
1739 return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs; in isPerfectIncrement()
1742 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD() argument
1746 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range"); in SelectVLD()
1759 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
1782 if (NumVecs == 1) in SelectVLD()
1785 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLD()
1802 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1809 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs); in SelectVLD()
1861 if (NumVecs == 1) { in SelectVLD()
1872 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) in SelectVLD()
1875 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1)); in SelectVLD()
1877 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2)); in SelectVLD()
1881 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST() argument
1885 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range"); in SelectVST()
1901 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVST()
1933 if (is64BitVector || NumVecs <= 2) { in SelectVST()
1935 if (NumVecs == 1) { in SelectVST()
1941 if (NumVecs == 2) in SelectVST()
1947 SDValue V3 = (NumVecs == 3) in SelectVST()
1965 bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs); in SelectVST()
1998 SDValue V3 = (NumVecs == 3) in SelectVST()
2033 unsigned NumVecs, in SelectVLDSTLane() argument
2036 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range"); in SelectVLDSTLane()
2051 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue(); in SelectVLDSTLane()
2056 if (NumVecs != 3) { in SelectVLDSTLane()
2058 unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8; in SelectVLDSTLane()
2086 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDSTLane()
2105 isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs); in SelectVLDSTLane()
2112 if (NumVecs == 2) { in SelectVLDSTLane()
2119 SDValue V3 = (NumVecs == 3) in SelectVLDSTLane()
2148 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) in SelectVLDSTLane()
2151 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1)); in SelectVLDSTLane()
2153 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2)); in SelectVLDSTLane()
2158 bool isUpdating, unsigned NumVecs, in SelectVLDDup() argument
2162 assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range"); in SelectVLDDup()
2175 if (NumVecs != 3) { in SelectVLDDup()
2177 unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8; in SelectVLDDup()
2204 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; in SelectVLDDup()
2219 if (is64BitVector || NumVecs == 1) { in SelectVLDDup()
2230 isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs); in SelectVLDDup()
2231 if (NumVecs <= 2 && !IsImmUpdate) in SelectVLDDup()
2236 else if (NumVecs > 2) in SelectVLDDup()
2243 } else if (NumVecs == 2) { in SelectVLDDup()
2269 if (NumVecs == 1) { in SelectVLDDup()
2275 for (unsigned Vec = 0; Vec != NumVecs; ++Vec) { in SelectVLDDup()
2280 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1)); in SelectVLDDup()
2282 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2)); in SelectVLDDup()