Searched refs:NextReg (Results 1 – 4 of 4) sorted by relevance
1228 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills() local1239 .addReg(NextReg) in emitAlignedDPRCS2Spills()1242 NextReg += 4; in emitAlignedDPRCS2Spills()1258 .addReg(NextReg) in emitAlignedDPRCS2Spills()1261 NextReg += 4; in emitAlignedDPRCS2Spills()1275 NextReg += 2; in emitAlignedDPRCS2Spills()1281 MBB.addLiveIn(NextReg); in emitAlignedDPRCS2Spills()1284 .addReg(NextReg) in emitAlignedDPRCS2Spills()1373 NextReg += 4; in emitAlignedDPRCS2Restores()1390 NextReg += 4; in emitAlignedDPRCS2Restores()[all …]
1654 unsigned NextReg = CSI[i + 1].getReg(); in computeCalleeSaveRegisterPairs() local1657 if (AArch64::GPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()1658 !invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI)) in computeCalleeSaveRegisterPairs()1659 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()1662 if (AArch64::FPR64RegClass.contains(NextReg) && in computeCalleeSaveRegisterPairs()1663 !invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI)) in computeCalleeSaveRegisterPairs()1664 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()1667 if (AArch64::FPR128RegClass.contains(NextReg)) in computeCalleeSaveRegisterPairs()1668 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
869 unsigned NextReg = SrcReg; in getSrcVReg() local872 NextReg = getIncomingRegForBlock(Inst, BB1); in getSrcVReg()877 NextReg = Inst->getOperand(1).getReg(); in getSrcVReg()878 if (NextReg == SrcReg || !TargetRegisterInfo::isVirtualRegister(NextReg)) in getSrcVReg()880 SrcReg = NextReg; in getSrcVReg()
5525 int NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg()); in ConvertXWPOperands() local5526 Inst.addOperand(MCOperand::createReg(NextReg)); in ConvertXWPOperands()