Lines Matching refs:NextReg

1228   unsigned NextReg = ARM::D8;  in emitAlignedDPRCS2Spills()  local
1233 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1239 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1242 NextReg += 4; in emitAlignedDPRCS2Spills()
1248 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Spills()
1252 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1258 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1261 NextReg += 4; in emitAlignedDPRCS2Spills()
1267 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1275 NextReg += 2; in emitAlignedDPRCS2Spills()
1281 MBB.addLiveIn(NextReg); in emitAlignedDPRCS2Spills()
1284 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1286 .addImm((NextReg - R4BaseReg) * 2) in emitAlignedDPRCS2Spills()
1361 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Restores() local
1365 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1367 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg) in emitAlignedDPRCS2Restores()
1373 NextReg += 4; in emitAlignedDPRCS2Restores()
1379 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Restores()
1383 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1385 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg) in emitAlignedDPRCS2Restores()
1390 NextReg += 4; in emitAlignedDPRCS2Restores()
1396 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Restores()
1402 NextReg += 2; in emitAlignedDPRCS2Restores()
1408 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg) in emitAlignedDPRCS2Restores()
1410 .addImm(2 * (NextReg - R4BaseReg)) in emitAlignedDPRCS2Restores()