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Searched refs:NewVT (Results 1 – 20 of 20) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp893 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); in getVectorTypeBreakdownMVT() local
894 if (!TLI->isTypeLegal(NewVT)) in getVectorTypeBreakdownMVT()
895 NewVT = EltTy; in getVectorTypeBreakdownMVT()
896 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
898 unsigned NewVTSize = NewVT.getSizeInBits(); in getVectorTypeBreakdownMVT()
904 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT()
1327 if (!isTypeLegal(NewVT)) in getVectorTypeBreakdown()
1328 NewVT = EltTy; in getVectorTypeBreakdown()
1329 IntermediateVT = NewVT; in getVectorTypeBreakdown()
1331 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown()
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypesGeneric.cpp222 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandRes_EXTRACT_VECTOR_ELT() local
235 NewVT, 2*OldElts), in ExpandRes_EXTRACT_VECTOR_ELT()
242 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
246 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
380 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); in ExpandOp_BUILD_VECTOR() local
400 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NewElts.size()); in ExpandOp_BUILD_VECTOR()
H A DLegalizeVectorTypes.cpp252 NewVT, Op); in ScalarizeVecRes_BITCAST()
1570 EVT NewVT = Inputs[0].getValueType(); in SplitVecRes_VECTOR_SHUFFLE() local
1628 EVT EltVT = NewVT.getVectorElementType(); in SplitVecRes_VECTOR_SHUFFLE()
1658 Output = DAG.getUNDEF(NewVT); in SplitVecRes_VECTOR_SHUFFLE()
3852 if (TLI.isTypeLegal(NewVT)) { in WidenVecOp_BITCAST()
4187 int NewVTWidth = NewVT.getSizeInBits(); in GenWidenVectorLoads()
4194 if (!NewVT.isVector()) { in GenWidenVectorLoads()
4200 if (NewVT == WidenVT) in GenWidenVectorLoads()
4206 SDValue UndefVal = DAG.getUNDEF(NewVT); in GenWidenVectorLoads()
4229 NewVTWidth = NewVT.getSizeInBits(); in GenWidenVectorLoads()
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H A DDAGCombiner.cpp3574 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHS()
3577 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); in visitMULHS()
3578 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
3631 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitMULHU()
3634 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); in visitMULHU()
3635 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
3707 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitSMUL_LOHI()
3712 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitSMUL_LOHI()
3738 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { in visitUMUL_LOHI()
3743 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitUMUL_LOHI()
[all …]
H A DSelectionDAG.cpp5578 EVT NewVT = VT; in FindOptimalMemOpLowering() local
5583 NewVT = (VT.getSizeInBits() > 64) ? MVT::i64 : MVT::i32; in FindOptimalMemOpLowering()
5584 if (TLI.isOperationLegalOrCustom(ISD::STORE, NewVT) && in FindOptimalMemOpLowering()
5585 TLI.isSafeMemOpType(NewVT.getSimpleVT())) in FindOptimalMemOpLowering()
5587 else if (NewVT == MVT::i64 && in FindOptimalMemOpLowering()
5591 NewVT = MVT::f64; in FindOptimalMemOpLowering()
5598 NewVT = (MVT::SimpleValueType)(NewVT.getSimpleVT().SimpleTy - 1); in FindOptimalMemOpLowering()
5599 if (NewVT == MVT::i8) in FindOptimalMemOpLowering()
5601 } while (!TLI.isSafeMemOpType(NewVT.getSimpleVT())); in FindOptimalMemOpLowering()
5603 NewVTSize = NewVT.getSizeInBits() / 8; in FindOptimalMemOpLowering()
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H A DLegalizeDAG.cpp2931 EVT NewVT = in ExpandNode() local
2934 assert(NewVT.bitsEq(VT)); in ExpandNode()
2937 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode()
2938 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode()
2942 NewVT.getVectorNumElements()/VT.getVectorNumElements(); in ExpandNode()
2958 VT = NewVT; in ExpandNode()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h308 EVT NewVT) const override;
H A DHexagonISelLowering.cpp3092 ISD::LoadExtType ExtTy, EVT NewVT) const { in shouldReduceLoadWidth()
3094 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h320 EVT NewVT) const override;
H A DAArch64ISelLowering.cpp2339 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts); in LowerVectorFP_TO_INT() local
2343 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
2535 EVT NewVT = getExtensionTo64Bits(OrigTy); in addRequiredExtensionForVectorMULL() local
2537 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in addRequiredExtensionForVectorMULL()
8128 EVT NewVT) const { in shouldReduceLoadWidth()
8130 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT)) in shouldReduceLoadWidth()
9621 MVT NewVT = MVT::getVectorVT(ElementTy, NumElems * 2); in tryExtendDUPToExtractHigh() local
9625 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()), in tryExtendDUPToExtractHigh()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp657 EVT NewVT) const { in shouldReduceLoadWidth()
659 if (!TargetLoweringBase::shouldReduceLoadWidth(N, ExtTy, NewVT)) in shouldReduceLoadWidth()
662 unsigned NewSize = NewVT.getStoreSizeInBits(); in shouldReduceLoadWidth()
2831 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performLoadCombine() local
2834 = DAG.getLoad(NewVT, SL, LN->getChain(), in performLoadCombine()
2881 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in performStoreCombine() local
2887 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val); in performStoreCombine()
H A DR600ISelLowering.cpp1821 EVT NewVT = MVT::v4i32; in constBufferLoad() local
1824 NewVT = VT; in constBufferLoad()
1827 SDValue Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements)); in constBufferLoad()
H A DSIISelLowering.cpp3877 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT); in ReplaceNodeResults() local
3878 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1)); in ReplaceNodeResults()
3879 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2)); in ReplaceNodeResults()
3881 EVT SelectVT = NewVT; in ReplaceNodeResults()
3882 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults()
3891 if (NewVT != SelectVT) in ReplaceNodeResults()
3892 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect); in ReplaceNodeResults()
4975 EVT NewVT = NumVDataDwords > 1 ? in lowerImage() local
4979 ResultTypes[0] = NewVT; in lowerImage()
8338 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VecVT); in performExtractVectorEltCombine() local
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H A DAMDGPUISelDAGToDAG.cpp646 MVT NewVT = Opc == AMDGPUISD::CVT_PKRTZ_F16_F32 ? MVT::v2f16 : MVT::v2i16; in Select() local
647 N = CurDAG->MorphNodeTo(N, N->getOpcode(), CurDAG->getVTList(NewVT), in Select()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetLowering.h1259 EVT NewVT) const { in shouldReduceLoadWidth() argument
1262 if (NewVT.isVector() && !Load->hasOneUse()) in shouldReduceLoadWidth()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp8009 MVT NewVT = V0_LO.getSimpleValueType(); in ExpandHorizontalBinOp() local
8011 SDValue LO = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
8012 SDValue HI = DAG.getUNDEF(NewVT); in ExpandHorizontalBinOp()
11456 MVT NewVT = V.getSimpleValueType(); in getScalarValueForVectorElement() local
11457 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) in getScalarValueForVectorElement()
16123 V1 = DAG.getBitcast(NewVT, V1); in lowerVectorShuffle()
16124 V2 = DAG.getBitcast(NewVT, V2); in lowerVectorShuffle()
19267 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); in Lower256IntVSETCC() local
23290 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) && in LowerVectorCTLZ_AVX512CDI()
23499 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); in split256IntArith() local
[all …]
H A DX86ISelLowering.h1031 EVT NewVT) const override;
/freebsd-12.1/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp3301 VectorType *NewVT = cast<VectorType>(II->getType()); in visitCallInst() local
3304 CV0 = ConstantExpr::getIntegerCast(CV0, NewVT, /*isSigned=*/!Zext); in visitCallInst()
3305 CV1 = ConstantExpr::getIntegerCast(CV1, NewVT, /*isSigned=*/!Zext); in visitCallInst()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12047 EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32; in combineElementTruncationToVectorTruncation() local
12048 SDValue BV = DAG.getBuildVector(NewVT, dl, Ops); in combineElementTruncationToVectorTruncation()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp7259 EVT NewVT = getExtensionTo64Bits(OrigTy); in AddRequiredExtensionForVMULL() local
7261 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in AddRequiredExtensionForVMULL()