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Searched refs:MaskedValueIsZero (Results 1 – 25 of 33) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombineShifts.cpp105 if (IC.MaskedValueIsZero(InnerShift->getOperand(0), Mask, 0, CxtI)) in canEvaluateShiftedShift()
146 if (MaskedValueIsZero(I->getOperand(0), in canEvaluateShifted()
615 MaskedValueIsZero(X, APInt::getHighBitsSet(SrcWidth, ShAmt), 0, &I)) in visitShl()
658 MaskedValueIsZero(Op0, APInt::getHighBitsSet(BitWidth, ShAmt), 0, &I)) { in visitShl()
807 MaskedValueIsZero(Op0, APInt::getLowBitsSet(BitWidth, ShAmt), 0, &I)) { in visitLShr()
892 MaskedValueIsZero(Op0, APInt::getLowBitsSet(BitWidth, ShAmt), 0, &I)) { in visitAShr()
899 if (MaskedValueIsZero(Op0, APInt::getSignMask(BitWidth), 0, &I)) in visitAShr()
H A DInstCombineCasts.cpp369 if (IC.MaskedValueIsZero(I->getOperand(0), Mask, 0, CxtI) && in canEvaluateTruncated()
370 IC.MaskedValueIsZero(I->getOperand(1), Mask, 0, CxtI)) { in canEvaluateTruncated()
396 IC.MaskedValueIsZero(I->getOperand(0), in canEvaluateTruncated()
561 if (!MaskedValueIsZero(ShVal, HiBitMask, 0, &Trunc)) in narrowRotate()
1017 if (IC.MaskedValueIsZero(I->getOperand(1), in canEvaluateZExtd()
1127 if (MaskedValueIsZero(Res, in visitZExt()
H A DInstCombineMulDivRem.cpp1023 if (MaskedValueIsZero(Op0, Mask, 0, &I)) { in visitSDiv()
1024 if (MaskedValueIsZero(Op1, Mask, 0, &I)) { in visitSDiv()
1311 if (MaskedValueIsZero(Op1, Mask, 0, &I) && in visitSRem()
1312 MaskedValueIsZero(Op0, Mask, 0, &I)) { in visitSRem()
H A DInstCombineAndOrXor.cpp1599 if (MaskedValueIsZero(X, NotAndMask, 0, &I)) { in visitAnd()
1605 if (!isa<Constant>(Y) && MaskedValueIsZero(Y, NotAndMask, 0, &I)) { in visitAnd()
2230 !CV->isAllOnesValue() && MaskedValueIsZero(Y, *CV, 0, &I)) { in visitOr()
2251 MaskedValueIsZero(V2, ~C1->getValue(), 0, &I)) || // (V|N) in visitOr()
2253 MaskedValueIsZero(V1, ~C1->getValue(), 0, &I)))) // (N|V) in visitOr()
2259 MaskedValueIsZero(V2, ~C2->getValue(), 0, &I)) || // (V|N) in visitOr()
2261 MaskedValueIsZero(V1, ~C2->getValue(), 0, &I)))) // (N|V) in visitOr()
2811 MaskedValueIsZero(X, *C, 0, &I)) { in visitXor()
H A DInstCombineInternal.h689 bool MaskedValueIsZero(const Value *V, const APInt &Mask, unsigned Depth = 0,
691 return llvm::MaskedValueIsZero(V, Mask, DL, Depth, &AC, CxtI, &DT);
H A DInstCombineAddSub.cpp1075 if (!MaskedValueIsZero(XorLHS, Mask, 0, &I)) in visitAdd()
H A DInstCombineVectorOps.cpp1278 if (match(BO1, m_APInt(C)) && MaskedValueIsZero(BO0, *C, DL)) in getAlternateBinop()
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreSelectionDAGInfo.cpp26 DAG.MaskedValueIsZero(Size, APInt(SizeBitWidth, 3))) { in EmitTargetCodeForMemcpy()
H A DXCoreISelLowering.cpp673 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) && in TryExpandADDWithMul()
674 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) { in TryExpandADDWithMul()
1753 DAG.MaskedValueIsZero(Mul0, HighMask) && in PerformDAGCombine()
1754 DAG.MaskedValueIsZero(Mul1, HighMask) && in PerformDAGCombine()
1755 DAG.MaskedValueIsZero(Addend0, HighMask) && in PerformDAGCombine()
1756 DAG.MaskedValueIsZero(Addend1, HighMask)) { in PerformDAGCombine()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp108 if (DAG.MaskedValueIsZero(Base->getOperand(0), C->getAPIntValue())) { in match()
H A DDAGCombiner.cpp4131 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { in visitANDLike()
4570 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), in visitAND()
4598 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { in visitAND()
4782 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, in visitAND()
4925 !DAG.MaskedValueIsZero( in MatchBSwapHWordLow()
5274 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) in visitOR()
6429 if (DAG.MaskedValueIsZero(N1, ModuloMask)) in visitRotate()
6517 if (DAG.MaskedValueIsZero(SDValue(N, 0), in visitSHL()
6883 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), in visitSRL()
7078 if (DAG.MaskedValueIsZero( in visitFunnelShift()
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H A DTargetLowering.cpp2541 if (DAG.MaskedValueIsZero(N0, in SimplifySetCC()
2946 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) in SimplifySetCC()
4076 if (DAG.MaskedValueIsZero(LHS, HighMask) && in expandMUL_LOHI()
4077 DAG.MaskedValueIsZero(RHS, HighMask)) { in expandMUL_LOHI()
H A DSelectionDAG.cpp2082 if (MaskedValueIsZero(V.getOperand(0), Mask)) in GetDemandedBits()
2084 if (MaskedValueIsZero(V.getOperand(1), Mask)) in GetDemandedBits()
2140 return MaskedValueIsZero(Op, APInt::getSignMask(BitWidth), Depth); in SignBitIsZero()
2146 bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, in MaskedValueIsZero() function in SelectionDAG
3806 !MaskedValueIsZero(Op.getOperand(0), in isBaseWithConstantOffset()
H A DSelectionDAGISel.cpp2185 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) in CheckAndMask()
/freebsd-12.1/contrib/llvm/include/llvm/Analysis/
H A DValueTracking.h157 bool MaskedValueIsZero(const Value *V, const APInt &Mask,
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp233 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { in MatchAddress()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td622 return CurDAG->MaskedValueIsZero(N->getOperand(0),
630 return CurDAG->MaskedValueIsZero(N->getOperand(1),
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrMemory.td34 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
/freebsd-12.1/contrib/llvm/lib/Analysis/
H A DValueTracking.cpp287 static bool MaskedValueIsZero(const Value *V, const APInt &Mask, unsigned Depth,
290 bool llvm::MaskedValueIsZero(const Value *V, const APInt &Mask, in MaskedValueIsZero() function in llvm
294 return ::MaskedValueIsZero( in MaskedValueIsZero()
2226 bool MaskedValueIsZero(const Value *V, const APInt &Mask, unsigned Depth, in MaskedValueIsZero() function
H A DBasicAliasAnalysis.cpp280 if (!MaskedValueIsZero(BOp->getOperand(0), RHSC->getValue(), DL, 0, AC, in GetLinearExpression()
H A DInstructionSimplify.cpp2027 if (MaskedValueIsZero(N, *C2, Q.DL, 0, Q.AC, Q.CxtI, Q.DT)) in SimplifyOrInst()
2034 if (MaskedValueIsZero(N, *C1, Q.DL, 0, Q.AC, Q.CxtI, Q.DT)) in SimplifyOrInst()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1427 bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1594 if (DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) && in LowerUDIVREM64()
1595 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) { in LowerUDIVREM64()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp9162 if (DAG.MaskedValueIsZero(CmpOp, HighBits)) in LowerATOMIC_CMP_SWAP()
11400 if (!DAG.MaskedValueIsZero(N->getOperand(0), in DAGCombineTruncBoolExt()
11402 !DAG.MaskedValueIsZero(N->getOperand(1), in DAGCombineTruncBoolExt()
11791 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0), in DAGCombineExtBoolTrunc()
13054 if (DAG.MaskedValueIsZero(Add->getOperand(1), in PerformDAGCombine()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp6685 if ((!N0.isUndef() && !DAG.MaskedValueIsZero(N0, ZeroMask)) || in getFauxShuffleMask()
6686 (!N1.isUndef() && !DAG.MaskedValueIsZero(N1, ZeroMask))) in getFauxShuffleMask()
10135 if ((N1.isUndef() || DAG.MaskedValueIsZero(VV1, ZeroMask)) && in matchVectorShuffleWithPACK()
10136 (N2.isUndef() || DAG.MaskedValueIsZero(VV2, ZeroMask))) { in matchVectorShuffleWithPACK()
19185 DAG.MaskedValueIsZero(BitNo, APInt(BitNo.getValueSizeInBits(), 32))) in LowerAndToBT()
35290 if (!DAG.MaskedValueIsZero(N1, Mask17) || in combineMulToPMADDWD()
35291 !DAG.MaskedValueIsZero(N0, Mask17)) in combineMulToPMADDWD()
35335 if (DAG.MaskedValueIsZero(N0, Mask) && DAG.MaskedValueIsZero(N1, Mask)) { in combineMulToPMULDQ()
35750 DAG.MaskedValueIsZero(N0, APInt::getHighBitsSet(16, 8)))) { in combineVectorPack()
36371 if (DAG.MaskedValueIsZero(N->getOperand(1), HiMask) || in combineAnd()
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