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Searched refs:MachineRegisterInfo (Results 1 – 25 of 322) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp43 void MachineRegisterInfo::Delegate::anchor() {} in anchor()
45 MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF) in MachineRegisterInfo() function in MachineRegisterInfo
64 void MachineRegisterInfo::setRegBank(unsigned Reg, in setRegBank()
70 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, in constrainRegClass()
86 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass()
93 MachineRegisterInfo::constrainRegAttrs(unsigned Reg, in constrainRegAttrs()
123 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { in recomputeRegClass()
203 void MachineRegisterInfo::clearVirtRegs() { in clearVirtRegs()
256 void MachineRegisterInfo::verifyUseLists() const { in verifyUseLists()
436 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { in isLiveIn()
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H A DMIRCanonicalizerPass.cpp241 MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo(); in rescheduleCanonically()
323 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in propagateLocalCopies()
368 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); in populateCandidates()
402 const MachineRegisterInfo &MRI = MF.getRegInfo(); in doCandidateWalk()
473 MachineRegisterInfo &MRI;
477 NamedVRegCursor(MachineRegisterInfo &MRI) : MRI(MRI) { in NamedVRegCursor()
519 MachineRegisterInfo &MRI, NamedVRegCursor &NVC) { in GetVRegRenameMap()
587 MachineRegisterInfo &MRI) { in doVRegRenaming()
663 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnBasicBlock()
796 MachineRegisterInfo &MRI = MF.getRegInfo(); in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h28 class MachineRegisterInfo; variable
44 unsigned constrainRegToClass(MachineRegisterInfo &MRI,
59 MachineRegisterInfo &MRI,
80 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
94 const MachineRegisterInfo &MRI);
96 const MachineRegisterInfo &MRI);
102 const MachineRegisterInfo &MRI);
113 const MachineRegisterInfo &MRI);
H A DMIPatternMatch.h25 bool mi_match(Reg R, MachineRegisterInfo &MRI, Pattern &&P) { in mi_match()
35 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { in match()
48 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { in match()
66 bool match(const MachineRegisterInfo &MRI, MachineOperand *MO) { in match()
76 bool match(MachineRegisterInfo &MRI, MatchSrc &&src) { in match()
88 bool match(MachineRegisterInfo &MRI, MatchSrc &&src) {
95 bool match(MachineRegisterInfo &MRI, MatchSrc &&src) {
106 bool match(MachineRegisterInfo &MRI, MatchSrc &&src) {
127 static bool bind(const MachineRegisterInfo &MRI, MachineInstr *&MI,
146 static bool bind(const MachineRegisterInfo &MRI, const ConstantFP *&F,
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H A DCombinerHelper.h25 class MachineRegisterInfo; variable
31 MachineRegisterInfo &MRI;
38 void replaceRegWith(MachineRegisterInfo &MRI, unsigned FromReg, unsigned ToReg) const;
42 void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp,
H A DRegisterBankInfo.h30 class MachineRegisterInfo; variable
288 MachineRegisterInfo &MRI;
322 MachineRegisterInfo &MRI);
333 MachineRegisterInfo &getMRI() const { return MRI; } in getMRI()
583 const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
630 MachineRegisterInfo &MRI);
714 unsigned getSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI,
H A DInstructionSelector.h39 class MachineRegisterInfo; variable
411 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
447 const MachineRegisterInfo &MRI) const;
453 const MachineRegisterInfo &MRI) const;
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.h28 class MachineRegisterInfo; variable
130 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
133 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
136 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
139 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
142 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
145 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
148 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
151 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
154 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
H A DRDFDeadCode.h32 class MachineRegisterInfo; variable
36 DeadCodeElimination(DataFlowGraph &dfg, MachineRegisterInfo &mri) in DeadCodeElimination()
54 MachineRegisterInfo &MRI;
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.h26 class MachineRegisterInfo; variable
60 const MachineRegisterInfo &MRI);
83 static unsigned getRegKind(unsigned Reg, const MachineRegisterInfo &MRI);
105 mutable const MachineRegisterInfo *MRI = nullptr;
131 const MachineRegisterInfo &MRI);
188 const MachineRegisterInfo &MRI);
192 const MachineRegisterInfo &MRI);
207 GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI, in getRegPressure()
217 const MachineRegisterInfo &MRI);
H A DSIRegisterInfo.h26 class MachineRegisterInfo; variable
141 bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const { in isSGPRReg()
188 unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
195 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
197 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
229 const MachineRegisterInfo &MRI) const override;
234 MachineRegisterInfo &MRI,
H A DSIInstrInfo.h41 class MachineRegisterInfo; variable
69 MachineRegisterInfo &MRI,
118 MachineRegisterInfo &MRI,
303 MachineRegisterInfo *MRI) const final;
621 const MachineRegisterInfo &MRI = MF.getRegInfo(); in isVGPRCopy()
705 bool usesConstantBus(const MachineRegisterInfo &MRI,
718 const MachineRegisterInfo &MRI) const;
789 bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
795 bool isLegalRegOperand(const MachineRegisterInfo &MRI,
936 MachineRegisterInfo &MRI) { in isOfRegClass()
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H A DGCNRegPressure.cpp39 const MachineRegisterInfo &MRI) { in printLivesAt()
86 const MachineRegisterInfo &MRI) { in getRegKind()
98 const MachineRegisterInfo &MRI) { in inc()
194 const MachineRegisterInfo &MRI) { in getDefRegMask()
207 const MachineRegisterInfo &MRI, in getUsedRegMask()
228 const MachineRegisterInfo &MRI) { in collectVirtualRegUses()
256 const MachineRegisterInfo &MRI) { in getLiveLaneMask()
274 const MachineRegisterInfo &MRI) { in getLiveRegs()
496 const MachineRegisterInfo &MRI) { in printLiveRegs()
H A DR600OptimizeVectorRegisters.cpp61 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) { in isImplicitlyDef()
62 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), in isImplicitlyDef()
81 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) { in RegSeqInfo()
104 MachineRegisterInfo *MRI;
241 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), in RebuildVector()
289 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg), in areAllUsesSwizzeable()
360 for (MachineRegisterInfo::def_instr_iterator in runOnMachineFunction()
H A DAMDGPUInstructionSelector.cpp66 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectCOPY()
88 MachineRegisterInfo &MRI = MF->getRegInfo(); in getSubOperand64()
124 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_ADD()
171 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_IMPLICIT_DEF()
195 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_INTRINSIC()
239 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_INTRINSIC_W_SIDE_EFFECTS()
282 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_STORE()
324 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectG_CONSTANT()
393 const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const { in getAddrModeInfo()
521 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectSMRD()
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/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp57 MachineRegisterInfo &MRI) { in IsRegInClass()
67 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
71 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
75 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
79 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
83 bool IsVSSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSSReg()
91 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in processBlock()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp86 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
88 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
90 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
92 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
94 bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
103 bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
117 bool selectShift(MachineInstr &I, MachineRegisterInfo &MRI,
119 bool selectDivRem(MachineInstr &I, MachineRegisterInfo &MRI,
319 MachineRegisterInfo &MRI = MF.getRegInfo(); in select()
479 const MachineRegisterInfo &MRI, in X86SelectAddress()
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H A DX86DomainReassignment.cpp104 MachineRegisterInfo *MRI) const = 0;
108 MachineRegisterInfo *MRI) const = 0;
119 MachineRegisterInfo *MRI) const override { in convertInstr()
125 MachineRegisterInfo *MRI) const override { in getExtraCost()
153 MachineRegisterInfo *MRI) const override { in convertInstr()
165 MachineRegisterInfo *MRI) const override { in getExtraCost()
181 MachineRegisterInfo *MRI) const override { in convertInstr()
201 MachineRegisterInfo *MRI) const override { in getExtraCost()
238 MachineRegisterInfo *MRI) const override { in getExtraCost()
269 MachineRegisterInfo *MRI) const override { in convertInstr()
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H A DX86CallLowering.cpp59 MachineRegisterInfo &MRI, in splitToValueTypes()
101 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in OutgoingValueHandler()
196 MachineRegisterInfo &MRI = MF.getRegInfo(); in lowerReturn()
229 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in IncomingValueHandler()
299 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in FormalArgHandler()
309 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in CallReturnHandler()
334 MachineRegisterInfo &MRI = MF.getRegInfo(); in lowerFormalArguments()
381 MachineRegisterInfo &MRI = MF.getRegInfo(); in lowerCall()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp67 MachineRegisterInfo *MRI;
106 const MachineRegisterInfo *MRI) { in isGPR64()
115 const MachineRegisterInfo *MRI) { in isFPR64()
129 const MachineRegisterInfo *MRI, in getSrcFromCopy()
210 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform()
223 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform()
242 for (MachineRegisterInfo::use_instr_nodbg_iterator in isProfitableToTransform()
303 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction()
322 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction()
H A DAArch64CallLowering.cpp55 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in IncomingArgHandler()
104 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in FormalArgHandler()
114 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in CallReturnHandler()
126 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in OutgoingArgHandler()
191 const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv, in splitToValueTypes()
241 MachineRegisterInfo &MRI = MF.getRegInfo(); in lowerReturn()
283 MachineRegisterInfo &MRI = MF.getRegInfo(); in lowerFormalArguments()
357 MachineRegisterInfo &MRI = MF.getRegInfo(); in lowerCall()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp31 unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass()
49 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass()
96 MachineRegisterInfo &MRI = MF.getRegInfo(); in constrainSelectedInstRegOperands()
136 const MachineRegisterInfo &MRI) { in isTriviallyDead()
186 const MachineRegisterInfo &MRI) { in getConstantVRegVal()
202 const MachineRegisterInfo &MRI) { in getConstantFPVRegVal()
210 const MachineRegisterInfo &MRI) { in getOpcodeDef()
240 const MachineRegisterInfo &MRI) { in ConstantFoldBinOp()
H A DInstructionSelector.cpp43 MachineRegisterInfo &MRI = MF.getRegInfo(); in constrainOperandRegToRegClass()
51 const MachineRegisterInfo &MRI) const { in isOperandImmEqual()
59 const MachineOperand &Root, const MachineRegisterInfo &MRI) const { in isBaseWithConstantOffset()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DRegisterPressure.h37 class MachineRegisterInfo; variable
164 const MachineRegisterInfo *MRI);
184 const MachineRegisterInfo &MRI, bool TrackLaneMasks,
196 const MachineRegisterInfo &MRI, SlotIndex Pos,
225 const MachineRegisterInfo &MRI);
295 void init(const MachineRegisterInfo &MRI);
364 const MachineRegisterInfo *MRI;
H A DVirtRegMap.h30 class MachineRegisterInfo; variable
43 MachineRegisterInfo *MRI;
88 MachineRegisterInfo &getRegInfo() const { return *MRI; } in getRegInfo()

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