| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandPseudoInsts.cpp | 183 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)); in tryToreplicateChunks()
207 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)); in tryToreplicateChunks()
357 AArch64_AM::getShifterImm(AArch64_AM::LSL, FirstMovkIdx * 16)); in trySequenceOfOnes()
373 AArch64_AM::getShifterImm(AArch64_AM::LSL, SecondMovkIdx * 16)); in trySequenceOfOnes()
471 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift)); in expandMOVImm()
555 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift)); in expandMOVImmSimple()
581 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift)); in expandMOVImmSimple()
831 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in expandMI()
967 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0), in expandMI()
972 AArch64_AM::getShifterImm(AArch64_AM::LSL, 0), in expandMI()
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| H A D | AArch64SchedPredicates.td | 49 def CheckShiftLSL : CheckImmOperand_s<3, "AArch64_AM::LSL">;
291 // ORR Rd, ZR, Rm, LSL #0
345 // MOVI Vd, #0, LSL #0
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| H A D | AArch64RegisterInfo.td | 1091 // LSL(8|16|32|64)
1092 def ZPR#RegWidth#AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", RegWidth, 8>;
1093 def ZPR#RegWidth#AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", RegWidth, 16>;
1094 def ZPR#RegWidth#AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", RegWidth, 32>;
1095 def ZPR#RegWidth#AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", RegWidth, 64>;
1096 def ZPR#RegWidth#ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 8>;
1097 def ZPR#RegWidth#ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 16>;
1098 def ZPR#RegWidth#ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 32>;
1099 def ZPR#RegWidth#ExtLSL64 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", RegWidth, 64>;
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| H A D | AArch64RegisterInfo.cpp | 415 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0); in materializeFrameBaseRegister()
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| H A D | AArch64InstrInfo.cpp | 775 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5; in isFalkorShiftExtFast()
2343 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)) in copyPhysReg()
2349 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in copyPhysReg()
2354 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in copyPhysReg()
2387 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in copyPhysReg()
2391 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); in copyPhysReg()
2925 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftSize)) in emitFrameOffset()
2941 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)) in emitFrameOffset()
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| H A D | AArch64FastISel.cpp | 708 Addr.setExtendType(AArch64_AM::LSL); in computeAddress()
792 Addr.setExtendType(AArch64_AM::LSL); in computeAddress()
837 Addr.setExtendType(AArch64_AM::LSL); in computeAddress()
1045 /*TODO:IsKill=*/false, AArch64_AM::LSL, in simplifyAddress()
1235 RHSIsKill, AArch64_AM::LSL, ShiftVal, SetFlags, in emitAddSub()
1249 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break; in emitAddSub()
1360 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1739 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitLogicalOp_rs()
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| H A D | AArch64FrameLowering.cpp | 959 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)) in emitPrologue()
967 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 16)) in emitPrologue()
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| H A D | AArch64ISelDAGToDAG.cpp | 283 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt); in SelectArithImmed()
330 return AArch64_AM::LSL; in getShiftTypeForNode()
1901 if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) { in getUsefulBitsFromOrWithShiftedReg()
2891 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0); in Select()
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| H A D | AArch64LoadStoreOptimizer.cpp | 919 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)) in promoteLoadFromStore()
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| H A D | AArch64SchedCyclone.td | 156 // EXAMPLE: ADDrs Xn, Xm LSL #imm
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 35 LSL = 0, enumerator
56 case AArch64_AM::LSL: return "lsl"; in getShiftExtendName()
77 case 0: return AArch64_AM::LSL; in getShiftType()
105 case AArch64_AM::LSL: STEnc = 0; break; in getShifterImm()
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| H A D | AArch64MCCodeEmitter.cpp | 265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
525 assert(AArch64_AM::getShiftType(ShiftOpnd) == AArch64_AM::LSL && in getImm8OptLsl()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1222 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isShifter()
1268 ET == AArch64_AM::LSL) && in isExtend()
1285 ET == AArch64_AM::LSL) && in isExtendLSL64()
1314 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isArithmeticShifter()
1336 if (ST != AArch64_AM::LSL) in isMovImm32Shifter()
1348 if (ST != AArch64_AM::LSL) in isMovImm64Shifter()
1360 return getShiftExtendType() == AArch64_AM::LSL && in isLogicalVecShifter()
1370 return getShiftExtendType() == AArch64_AM::LSL && in isLogicalVecHalfWordShifter()
1748 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
1756 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX; in addExtend64Operands()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 39 LSL, ///< Logical shift left. enumerator
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| H A D | AVRInstrInfo.td | 58 def AVRlsl : SDNode<"AVRISD::LSL", SDTIntUnaryOp>;
1635 // 8-bit LSL is an alias of ADD Rd, Rd
1753 // LSL Rd
1757 def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8:$rd, GPR8:$rd)>;
2104 // Lowering of 'lsl' node to 'LSL' instruction.
2105 // LSL is an alias of 'ADD Rd, Rd'
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| H A D | AVRISelLowering.cpp | 256 NODE(LSL); in getTargetNodeName()
327 Opc8 = AVRISD::LSL; in LowerShifts()
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| /freebsd-12.1/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM64/ |
| H A D | EmulateInstructionARM64.cpp | 81 static inline uint64_t LSL(uint64_t x, integer shift) { in LSL() function
781 idx = LSL(llvm::SignExtend64<7>(imm7), scale); in EmulateLDPSTP()
960 offset = LSL(Bits32(opcode, 21, 10), size); in EmulateLDRSTRImm()
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| /freebsd-12.1/contrib/gcc/config/arm/ |
| H A D | arm1026ejs.md | 164 ;; those that are base + offset with LSL of 0 or 2, or base - offset
165 ;; with LSL of zero. The remainder take 1 cycle to execute.
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| H A D | arm1020e.md | 164 ;; those that are base + offset with LSL of 0 or 2, or base - offset
165 ;; with LSL of zero. The remainder take 1 cycle to execute.
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| /freebsd-12.1/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/ |
| H A D | ARMUtils.h | 101 static inline uint32_t LSL(const uint32_t value, const uint32_t amount, in LSL() function
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 402 LSL, enumerator
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2508 LatticeCell LSL, LSH; in evaluateHexRSEQ32() local
2509 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH)) in evaluateHexRSEQ32()
2511 if (LSL.isProperty() || LSH.isProperty()) in evaluateHexRSEQ32()
2514 unsigned LN = LSL.size(), HN = LSH.size(); in evaluateHexRSEQ32()
2517 bool Eval = constToInt(LSL.Values[i], LoVs[i]); in evaluateHexRSEQ32()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/InstPrinter/ |
| H A D | AArch64InstPrinter.cpp | 956 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL && in printShifter()
1511 assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && in printImm8OptLsl()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMInstrThumb.td | 1120 // LSL immediate
1131 // LSL register
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| H A D | ARMScheduleSwift.td | 155 // ASR,LSL,ROR,RRX
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