Lines Matching refs:LSL
1169 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
1222 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isShifter()
1268 ET == AArch64_AM::LSL) && in isExtend()
1285 ET == AArch64_AM::LSL) && in isExtendLSL64()
1293 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) && in isMemXExtend()
1314 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isArithmeticShifter()
1325 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isLogicalShifter()
1336 if (ST != AArch64_AM::LSL) in isMovImm32Shifter()
1348 if (ST != AArch64_AM::LSL) in isMovImm64Shifter()
1360 return getShiftExtendType() == AArch64_AM::LSL && in isLogicalVecShifter()
1370 return getShiftExtendType() == AArch64_AM::LSL && in isLogicalVecHalfWordShifter()
1748 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW; in addExtendOperands()
1756 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX; in addExtend64Operands()
1827 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, in CreateReg()
1846 AArch64_AM::ShiftExtendType ExtTy = AArch64_AM::LSL, in CreateVectorReg()
2750 .Case("lsl", AArch64_AM::LSL) in tryParseOptionalShiftExtend()
2774 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
3695 Operands.push_back(AArch64Operand::CreateShiftExtend(AArch64_AM::LSL, in parseOperand()