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Searched refs:ImplicitDefine (Results 1 – 24 of 24) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp389 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
411 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
430 .addReg(ScratchRsrcReg, RegState::ImplicitDefine) in emitEntryFunctionScratchSetup()
453 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
471 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
479 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
483 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
489 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
493 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitEntryFunctionScratchSetup()
H A DSIRegisterInfo.cpp908 MIB.addReg(SuperReg, RegState::ImplicitDefine); in restoreSGPR()
922 MIB.addReg(SuperReg, RegState::ImplicitDefine); in restoreSGPR()
951 MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in restoreSGPR()
H A DSILowerControlFlow.cpp196 .addReg(AMDGPU::EXEC, RegState::ImplicitDefine); in emitIf()
H A DSIInstrInfo.cpp917 Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine | RegState::Dead); in storeRegToStackSlot()
1011 Spill.addReg(AMDGPU::M0, RegState::ImplicitDefine | RegState::Dead); in loadRegFromStackSlot()
1254 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
H A DSIISelLowering.cpp3207 .addReg(Dst, RegState::ImplicitDefine) in emitIndirectDst()
3241 .addReg(Dst, RegState::ImplicitDefine) in emitIndirectDst()
3459 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine) in EmitInstrWithCustomInserter()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZElimCompare.cpp239 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT()
574 RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
H A DSystemZShortenInst.cpp147 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
H A DSystemZFrameLowering.cpp277 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
H A DSystemZInstrInfo.cpp254 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h55 ImplicitDefine = Implicit | Define, enumerator
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp216 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
H A DARMExpandPseudoInsts.cpp569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
735 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
1598 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
H A DARMBaseInstrInfo.cpp1258 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1296 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1319 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1339 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
H A DARMFrameLowering.cpp1371 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
1388 .addReg(SupReg, RegState::ImplicitDefine) in emitAlignedDPRCS2Restores()
H A DARMLoadStoreOptimizer.cpp944 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
H A DARMISelLowering.cpp8691 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in EmitSjLjDispatchBlock()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp2138 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
2139 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
H A DMipsSEInstrInfo.cpp135 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp57 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; in addDSPCtrlRegOperands()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp918 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | in EmitMachineNode()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp4165 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
4193 MIB.addReg(SrcReg, RegState::ImplicitDefine); in expandPostRAPseudo()
4262 MIB.addReg(Reg, RegState::ImplicitDefine); in expandPostRAPseudo()
4605 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
4614 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
H A DX86ISelLowering.cpp28686 .addReg(X86::RAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
28694 .addReg(X86::EAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
28702 .addReg(X86::EAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
28843 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
28855 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
28867 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
29733 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in EmitSjLjDispatchBlock()
/freebsd-12.1/contrib/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp1133 Flags |= RegState::ImplicitDefine; in parseRegisterFlag()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2294 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()