Searched refs:ITState (Results 1 – 3 of 3) sorted by relevance
217 } ITState; member in __anonb936c2650111::ARMAsmParser243 ITState.Mask = 0; in flushPendingInstructions()252 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask); in lastInITBlock()261 if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit) in forwardITPosition()308 MaskBit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; in currentITCond()310 return MaskBit ? ITState.Cond : ARMCC::getOppositeCondition(ITState.Cond); in currentITCond()317 ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond); in invertCurrentITCondition()319 ITState.Mask ^= 1 << (5 - ITState.CurPosition); in invertCurrentITCondition()350 ITState.Mask = 8; in startImplicitITBlock()360 ITState.Cond = Cond; in startExplicitITBlock()[all …]
23 ITSession() : ITCounter(0), ITState(0) {} in ITSession()44 uint32_t ITState; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially. variable
638 ITState = bits7_0; in InitIT()647 ITState = 0; in ITAdvance()649 unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1; in ITAdvance()650 SetBits32(ITState, 4, 0, NewITState4_0); in ITAdvance()663 return Bits32(ITState, 7, 4); in GetCond()