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Searched refs:INSERT_SUBVECTOR (Results 1 – 15 of 15) sorted by relevance

/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h353 INSERT_SUBVECTOR, enumerator
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp713 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1857 setTargetDAGCombine(ISD::INSERT_SUBVECTOR); in X86TargetLowering()
6560 case ISD::INSERT_SUBVECTOR: { in getFauxShuffleMask()
9318 if (Opc == ISD::INSERT_SUBVECTOR) { in isTypePromotionOfi1ZeroUpBits()
11698 case ISD::INSERT_SUBVECTOR: { in lowerVectorShuffleAsBroadcast()
14014 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV2X128VectorShuffle()
15323 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lowerV4X128VectorShuffle()
15885 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in lower1BitVectorShuffle()
41200 if (SubVec.getOpcode() == ISD::INSERT_SUBVECTOR && in combineInsertSubvector()
41283 Vec.getOpcode() == ISD::INSERT_SUBVECTOR && in combineInsertSubvector()
[all …]
H A DX86ISelDAGToDAG.cpp639 if (Root->getOpcode() == ISD::INSERT_SUBVECTOR && in IsProfitableToFold()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp98 setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); in initializeHVXLowering()
189 setOperationAction(ISD::INSERT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
1555 case ISD::INSERT_SUBVECTOR: return LowerHvxInsertSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1432 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1477 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
2762 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp275 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
H A DDAGCombiner.cpp1588 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); in visit()
16137 VecIn2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, InVT1, in createBuildVecShuffle()
17127 if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
17989 SDValue NewINSERT = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), in visitINSERT_SUBVECTOR()
17998 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
18001 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0), in visitINSERT_SUBVECTOR()
18007 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && in visitINSERT_SUBVECTOR()
18009 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0, in visitINSERT_SUBVECTOR()
18021 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() && in visitINSERT_SUBVECTOR()
18027 SDValue NewOp = DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, in visitINSERT_SUBVECTOR()
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H A DLegalizeVectorTypes.cpp729 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
1046 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
3763 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp, in WidenVecOp_EXTEND()
H A DSelectionDAG.cpp2421 case ISD::INSERT_SUBVECTOR: { in computeKnownBits()
3714 case ISD::INSERT_SUBVECTOR: { in ComputeNumSignBits()
5091 if (N1.getOpcode() == ISD::INSERT_SUBVECTOR && N2 == N1.getOperand(2) && in getNode()
5319 case ISD::INSERT_SUBVECTOR: { in getNode()
H A DLegalizeDAG.cpp2897 case ISD::INSERT_SUBVECTOR: in ExpandNode()
H A DTargetLowering.cpp1613 case ISD::INSERT_SUBVECTOR: { in SimplifyDemandedVectorElts()
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td555 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp475 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR) in checkHighLaneIndex()
H A DAArch64ISelLowering.cpp5894 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy), in WidenVector()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp261 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
507 case ISD::INSERT_SUBVECTOR: in SITargetLowering()