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Searched refs:HasBaseReg (Results 1 – 21 of 21) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86AsmPrinter.cpp268 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference() local
269 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in printLeaMemReference()
271 HasBaseReg = false; in printLeaMemReference()
274 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
298 if (HasBaseReg) in printLeaMemReference()
H A DX86ISelLowering.cpp27433 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) in isLegalAddressingMode()
27455 if (AM.HasBaseReg) in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp323 bool HasBaseReg = false; member
443 HasBaseReg = true; in initialMatch()
449 HasBaseReg = true; in initialMatch()
593 if (HasBaseReg && BaseRegs.empty()) { in print()
596 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1775 bool HasBaseReg) { in isAlwaysFoldable() argument
1785 if (!HasBaseReg && Scale == 1) { in isAlwaysFoldable()
1787 HasBaseReg = true; in isAlwaysFoldable()
1798 bool HasBaseReg) { in isAlwaysFoldable() argument
3320 F.HasBaseReg = true; in InsertSupplementalFormula()
[all …]
/freebsd-12.1/contrib/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h239 bool HasBaseReg, int64_t Scale,
272 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { in getScalingFactorCost() argument
274 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
723 bool HasBaseReg = (BaseGV == nullptr); in getGEPCost() local
771 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale, AS)) in getGEPCost()
H A DTargetTransformInfo.h473 bool HasBaseReg, int64_t Scale,
525 bool HasBaseReg, int64_t Scale,
1061 int64_t BaseOffset, bool HasBaseReg,
1077 int64_t BaseOffset, bool HasBaseReg,
1289 bool HasBaseReg, int64_t Scale, in isLegalAddressingMode() argument
1292 return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
1327 bool HasBaseReg, int64_t Scale, in getScalingFactorCost() argument
1329 return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h227 bool HasBaseReg, int64_t Scale,
232 AM.HasBaseReg = HasBaseReg;
254 bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { in getScalingFactorCost() argument
258 AM.HasBaseReg = HasBaseReg; in getScalingFactorCost()
H A DTargetLowering.h2071 bool HasBaseReg = false; member
/freebsd-12.1/contrib/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp146 bool HasBaseReg, in isLegalAddressingMode() argument
150 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
197 bool HasBaseReg, in getScalingFactorCost() argument
200 int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, in getScalingFactorCost()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp249 AM.HasBaseReg = !AM.BaseGV; in visit()
H A DSILoadStoreOptimizer.cpp1369 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
1394 AM.HasBaseReg = true; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp1013 if (AM.HasBaseReg) { in isLegalMUBUFAddressingMode()
1070 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
1089 if (AM.Scale == 1 && AM.HasBaseReg) in isLegalAddressingMode()
7108 AM.HasBaseReg = true; in performSHLPtrCombine()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2985 !NewAddrMode.HasBaseReg); in addNewAddrMode()
4049 if (AddrMode.HasBaseReg) { in matchOperationAddr()
4054 AddrMode.HasBaseReg = true; in matchOperationAddr()
4065 if (AddrMode.HasBaseReg) in matchOperationAddr()
4067 AddrMode.HasBaseReg = true; in matchOperationAddr()
4200 if (!AddrMode.HasBaseReg) { in matchAddr()
4201 AddrMode.HasBaseReg = true; in matchAddr()
4206 AddrMode.HasBaseReg = false; in matchAddr()
H A DTargetLoweringBase.cpp1613 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1618 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp751 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) { in isLegalAddressingMode()
763 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 0 && isUInt<6>(Offs)) { in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp223 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp3964 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
3971 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1891 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13238 if (!AM.HasBaseReg && Scale == 2) in isLegalT2ScaledAddressingMode()
13264 return (Scale == 1) || (!AM.HasBaseReg && Scale == 2); in isLegalT1ScaledAddressingMode()
13311 if (Scale == 1 || (AM.HasBaseReg && Scale == -1)) in isLegalAddressingMode()
13314 if (!AM.HasBaseReg && Scale == 2) in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4045 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp13751 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
13756 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp8656 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()