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Searched refs:FirstReg (Results 1 – 10 of 10) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp373 unsigned FirstReg = 0; in CreateRegs() local
381 if (!FirstReg) FirstReg = R; in CreateRegs()
384 return FirstReg; in CreateRegs()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp506 unsigned FirstReg = 0; in ScanInstruction() local
513 if (FirstReg != 0) { in ScanInstruction()
515 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
518 FirstReg = Reg; in ScanInstruction()
522 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp2110 unsigned &FirstReg, in CanFormLdStDWord() argument
2172 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2174 if (FirstReg == SecondReg) in CanFormLdStDWord()
2276 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
2284 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2291 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2297 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2311 .addReg(FirstReg) in RescheduleOps()
2329 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2330 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3281 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadImmReal() local
3316 TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI); in expandLoadImmReal()
3339 TOut.emitRRX(Mips::LWC1, FirstReg, ATReg, in expandLoadImmReal()
3413 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, ATReg, IDLoc, STI); in expandLoadImmReal()
4105 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
4122 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4130 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4828 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadStoreDMacro() local
4829 unsigned SecondReg = nextReg(FirstReg); in expandLoadStoreDMacro()
4834 warnIfRegIndexIsAT(FirstReg, IDLoc); in expandLoadStoreDMacro()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp1269 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1270 Reg = FirstReg; in printVectorList()
1271 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1272 Reg = FirstReg; in printVectorList()
1273 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
1274 Reg = FirstReg; in printVectorList()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp4102 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
4134 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
4159 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
4173 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4222 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4297 unsigned FirstReg = 0; in HandleByVal() local
4313 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
4319 if ((Align > RegSizeInBytes) && (FirstReg % 2)) { in HandleByVal()
4320 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); in HandleByVal()
4321 ++FirstReg; in HandleByVal()
[all …]
H A DMipsISelLowering.h579 const Argument *FuncArg, unsigned FirstReg,
588 unsigned FirstReg, unsigned LastReg,
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1523 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
3335 unsigned FirstReg; in tryParseVectorList() local
3336 auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch); in tryParseVectorList()
3346 int64_t PrevReg = FirstReg; in tryParseVectorList()
5601 unsigned FirstReg; in tryParseGPRSeqPair() local
5602 OperandMatchResultTy Res = tryParseScalarRegister(FirstReg); in tryParseGPRSeqPair()
5611 bool isXReg = XRegClass.contains(FirstReg), in tryParseGPRSeqPair()
5612 isWReg = WRegClass.contains(FirstReg); in tryParseGPRSeqPair()
5620 unsigned FirstEncoding = RI->getEncodingValue(FirstReg); in tryParseGPRSeqPair()
5651 Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube64, in tryParseGPRSeqPair()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
849 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
850 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
852 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
854 unsigned OldFirstReg = FirstReg; in insertSelect()
855 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
856 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
861 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp4014 unsigned FirstReg = Reg; in parseVectorList() local
4018 FirstReg = Reg = getDRegFromQReg(Reg); in parseVectorList()
4160 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
4162 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, in parseVectorList()
4172 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
4174 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, in parseVectorList()
4179 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()