3281   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadImmReal()  local
3304       if (loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, true, IDLoc,  in expandLoadImmReal()
3316         TOut.emitRR(Mips::MTC1, FirstReg, ATReg, IDLoc, STI);  in expandLoadImmReal()
3339       TOut.emitRRX(Mips::LWC1, FirstReg, ATReg,  in expandLoadImmReal()
3353         if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, false, true,  in expandLoadImmReal()
3358         if (loadImmediate(HiImmOp64, FirstReg, Mips::NoRegister, true, true,  in expandLoadImmReal()
3362         if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, true,  in expandLoadImmReal()
3395       TOut.emitRRI(Mips::LD, FirstReg, ATReg, 0, IDLoc, STI);  in expandLoadImmReal()
3397       TOut.emitRRI(Mips::LW, FirstReg, ATReg, 0, IDLoc, STI);  in expandLoadImmReal()
3398       TOut.emitRRI(Mips::LW, nextReg(FirstReg), ATReg, 4, IDLoc, STI);  in expandLoadImmReal()
3410         TOut.emitRR(Mips::DMTC1, FirstReg, ATReg, IDLoc, STI);  in expandLoadImmReal()
3412         TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadImmReal()
3413         TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, ATReg, IDLoc, STI);  in expandLoadImmReal()
3415         TOut.emitRR(Mips::MTC1, nextReg(FirstReg), ATReg, IDLoc, STI);  in expandLoadImmReal()
3416         TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadImmReal()
3441     TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, ATReg,  in expandLoadImmReal()
4105   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandTrunc()  local
4122                 FirstReg, SecondReg, IDLoc, STI);  in expandTrunc()
4130               FirstReg, SecondReg, IDLoc, STI);  in expandTrunc()
4828   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadStoreDMacro()  local
4829   unsigned SecondReg = nextReg(FirstReg);  in expandLoadStoreDMacro()
4834   warnIfRegIndexIsAT(FirstReg, IDLoc);  in expandLoadStoreDMacro()
4848   if (FirstReg != BaseReg || !IsLoad) {  in expandLoadStoreDMacro()
4849     TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandLoadStoreDMacro()
4853     TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandLoadStoreDMacro()