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Searched refs:FalseReg (Results 1 – 18 of 18) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86CmovConversion.cpp715 unsigned FalseReg = in convertCmovInstsToBranches() local
720 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); in convertCmovInstsToBranches()
723 FalseReg = FRIt->second; in convertCmovInstsToBranches()
725 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; in convertCmovInstsToBranches()
H A DX86InstrInfo.h348 unsigned FalseReg) const override;
H A DX86InstrInfo.cpp2875 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
2889 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
2913 unsigned FalseReg) const { in insertSelect()
2921 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); in insertSelect()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp507 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
509 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
533 FalseReg.setImplicit(); in optimizeSelect()
534 NewMI.add(FalseReg); in optimizeSelect()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp745 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
784 unsigned FalseReg) const { in insertSelect()
843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
844 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
2222 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
2229 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
2231 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
2233 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
2245 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
2505 unsigned FalseReg = CompareUseMI.getOperand(2).getReg(); in convertToImmediateForm() local
[all …]
H A DPPCInstrInfo.h285 unsigned FalseReg) const override;
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp562 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
574 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
598 unsigned FalseReg) const { in insertSelect()
616 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
618 FalseReg = FReg; in insertSelect()
626 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZInstrInfo.h216 unsigned FalseReg) const override;
H A DSystemZISelLowering.cpp6260 unsigned FalseReg = MIIt->getOperand(2).getReg(); in createPHIsForSelects() local
6266 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
6271 if (RegRewriteTable.find(FalseReg) != RegRewriteTable.end()) in createPHIsForSelects()
6272 FalseReg = RegRewriteTable[FalseReg].second; in createPHIsForSelects()
6276 .addReg(FalseReg).addMBB(FalseMBB); in createPHIsForSelects()
6279 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h279 unsigned TrueReg, unsigned FalseReg,
286 unsigned TrueReg, unsigned FalseReg) const override;
291 unsigned TrueReg, unsigned FalseReg) const;
H A DSIInstrInfo.cpp707 .addReg(FalseReg) in insertVectorSelect()
719 .addReg(FalseReg) in insertVectorSelect()
730 .addReg(FalseReg) in insertVectorSelect()
742 .addReg(FalseReg) in insertVectorSelect()
755 .addReg(FalseReg) in insertVectorSelect()
768 .addReg(FalseReg) in insertVectorSelect()
782 .addReg(FalseReg) in insertVectorSelect()
1860 std::swap(TrueReg, FalseReg); in insertSelect()
1874 .addReg(FalseReg) in insertSelect()
1884 .addReg(FalseReg) in insertSelect()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp884 unsigned FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
885 if (FalseReg == 0) in selectSelect()
889 std::swap(TrueReg, FalseReg); in selectSelect()
924 .addReg(FalseReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp348 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
353 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
386 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); in LowerFPToInt()
390 .addReg(FalseReg) in LowerFPToInt()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp698 auto FalseReg = MIB->getOperand(3).getReg(); in selectSelect() local
700 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
705 .addUse(FalseReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2115 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); in optimizeSelect() local
2117 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
2147 FalseReg.setImplicit(); in optimizeSelect()
2148 NewMI.add(FalseReg); in optimizeSelect()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h759 unsigned FalseReg, int &CondCycles, in canInsertSelect() argument
782 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h179 unsigned FalseReg) const override;
H A DAArch64InstrInfo.cpp497 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
503 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
519 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
541 unsigned TrueReg, unsigned FalseReg) const { in insertSelect()
649 TrueReg = FalseReg; in insertSelect()
651 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
655 FalseReg = NewVReg; in insertSelect()
664 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
669 .addReg(FalseReg) in insertSelect()