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Searched refs:FSQRT (Results 1 – 25 of 39) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1867 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost()
1868 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/ in getIntrinsicInstrCost()
1875 { ISD::FSQRT, MVT::f32, 19 }, // sqrtss in getIntrinsicInstrCost()
1876 { ISD::FSQRT, MVT::v4f32, 37 }, // sqrtps in getIntrinsicInstrCost()
1877 { ISD::FSQRT, MVT::f64, 34 }, // sqrtsd in getIntrinsicInstrCost()
1878 { ISD::FSQRT, MVT::v2f64, 67 }, // sqrtpd in getIntrinsicInstrCost()
1881 { ISD::FSQRT, MVT::f32, 20 }, // sqrtss in getIntrinsicInstrCost()
1882 { ISD::FSQRT, MVT::v4f32, 40 }, // sqrtps in getIntrinsicInstrCost()
1883 { ISD::FSQRT, MVT::f64, 35 }, // sqrtsd in getIntrinsicInstrCost()
1884 { ISD::FSQRT, MVT::v2f64, 70 }, // sqrtpd in getIntrinsicInstrCost()
[all …]
H A DX86.td298 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
300 // vector FSQRT has higher throughput than the corresponding NR code.
H A DX86IntrinsicsInfo.h1009 X86_INTRINSIC_DATA(avx512_sqrt_pd_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
1010 X86_INTRINSIC_DATA(avx512_sqrt_ps_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
/freebsd-12.1/contrib/one-true-awk/
H A Dawk.h116 #define FSQRT 2 macro
H A Dlex.c87 { "sqrt", FSQRT, BLTIN },
H A Drun.c1502 case FSQRT: in bltin()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h584 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator
H A DBasicTTIImpl.h388 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
1155 ISDs.push_back(ISD::FSQRT);
H A DTargetLowering.h849 case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break; in getStrictFPOperationAction()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp327 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; in mightUseCTR()
372 Opcode = ISD::FSQRT; break; in mightUseCTR()
H A DPPCISelLowering.cpp289 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
294 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
601 setOperationAction(ISD::FSQRT, VT, Expand); in PPCTargetLowering()
674 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
730 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
1019 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); in PPCTargetLowering()
1022 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
1025 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand); in PPCTargetLowering()
1028 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in PPCTargetLowering()
1092 setTargetDAGCombine(ISD::FSQRT); in PPCTargetLowering()
H A DP9InstrResources.td1139 FSQRT
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td549 // FDIV,FSQRT
551 // TODO: Specialize FSQRT for longer latency.
H A DAArch64ISelLowering.cpp223 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in AArch64TargetLowering()
382 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in AArch64TargetLowering()
421 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand); in AArch64TargetLowering()
435 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand); in AArch64TargetLowering()
640 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand); in AArch64TargetLowering()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp187 case ISD::FSQRT: return "fsqrt"; in getOperationName()
H A DLegalizeFloatTypes.cpp103 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; in SoftenFloatResult()
1094 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; in ExpandFloatResult()
1906 case ISD::FSQRT: in PromoteFloatResult()
H A DLegalizeVectorOps.cpp392 case ISD::FSQRT: in LegalizeOp()
H A DLegalizeVectorTypes.cpp97 case ISD::FSQRT: in ScalarizeVectorResult()
783 case ISD::FSQRT: in SplitVectorResult()
2521 case ISD::FSQRT: in WidenVectorResult()
H A DDAGCombiner.cpp1558 case ISD::FSQRT: return visitFSQRT(N); in visit()
11644 if (N1.getOpcode() == ISD::FSQRT) { in visitFDIV()
11649 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
11657 N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
11669 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) { in visitFDIV()
11672 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) { in visitFDIV()
11857 if (!DAG.getTargetLoweringInfo().isOperationLegalOrCustom(ISD::FSQRT, VT)) in visitFPOW()
11867 SDValue Sqrt = DAG.getNode(ISD::FSQRT, DL, VT, N->getOperand(0), Flags); in visitFPOW()
11868 return DAG.getNode(ISD::FSQRT, DL, VT, Sqrt, Flags); in visitFPOW()
18247 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) { in SimplifySelectOps()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td124 defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
H A DMipsSEISelLowering.cpp151 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in MipsSETargetLowering()
389 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
1881 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
H A DMipsInstrFPU.td505 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1715 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1740 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1792 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
3044 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp225 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in WebAssemblyTargetLowering()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1377 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1422 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()

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