| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 185 { ISD::FDIV, MVT::f32, 18 }, // divss in getArithmeticInstrCost()
186 { ISD::FDIV, MVT::v4f32, 35 }, // divps in getArithmeticInstrCost()
187 { ISD::FDIV, MVT::f64, 33 }, // divsd in getArithmeticInstrCost()
188 { ISD::FDIV, MVT::v2f64, 65 }, // divpd in getArithmeticInstrCost()
203 { ISD::FDIV, MVT::f32, 17 }, // divss in getArithmeticInstrCost()
204 { ISD::FDIV, MVT::v4f32, 39 }, // divps in getArithmeticInstrCost()
205 { ISD::FDIV, MVT::f64, 32 }, // divsd in getArithmeticInstrCost()
206 { ISD::FDIV, MVT::v2f64, 69 }, // divpd in getArithmeticInstrCost()
766 { ISD::FDIV, MVT::f32, 14 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
767 { ISD::FDIV, MVT::v4f32, 14 }, // Nehalem from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
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| H A D | X86IntrinsicsInfo.h | 437 X86_INTRINSIC_DATA(avx512_div_pd_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
438 X86_INTRINSIC_DATA(avx512_div_ps_512, INTR_TYPE_2OP, ISD::FDIV, X86ISD::FDIV_RND),
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 283 FADD, FSUB, FMUL, FDIV, FREM, enumerator
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| H A D | SelectionDAGNodes.h | 2485 Op == ISD::FMUL || Op == ISD::FDIV || Op == ISD::FREM);
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| H A D | TargetLowering.h | 847 case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break; in getStrictFPOperationAction()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUTargetTransformInfo.cpp | 397 case ISD::FDIV: in getArithmeticInstrCost()
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| H A D | SIISelLowering.cpp | 418 setOperationAction(ISD::FDIV, MVT::f32, Custom); in SITargetLowering()
419 setOperationAction(ISD::FDIV, MVT::f64, Custom); in SITargetLowering()
491 setOperationAction(ISD::FDIV, MVT::f16, Custom); in SITargetLowering()
3636 case ISD::FDIV: return LowerFDIV(Op, DAG); in LowerOperation()
7603 case ISD::FDIV: in fp16SrcZerosHighBits()
7740 case ISD::FDIV: in isCanonicalized()
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| H A D | AMDGPUISelLowering.cpp | 449 setOperationAction(ISD::FDIV, VT, Expand); in AMDGPUTargetLowering()
592 case ISD::FDIV: in hasSourceMods()
1966 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y); in LowerFREM()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 873 void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); } in visitFDiv()
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| H A D | SelectionDAGDumper.cpp | 248 case ISD::FDIV: return "fdiv"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 83 case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break; in SoftenFloatResult()
1077 case ISD::FDIV: ExpandFloatRes_FDIV(N, Lo, Hi); break; in ExpandFloatResult()
1912 case ISD::FDIV: in PromoteFloatResult()
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| H A D | LegalizeVectorOps.cpp | 353 case ISD::FDIV: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 112 case ISD::FDIV: in ScalarizeVectorResult()
812 case ISD::FDIV: in SplitVectorResult()
2439 case ISD::FDIV: in WidenVectorResult()
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| H A D | SelectionDAG.cpp | 3833 case ISD::FDIV: in isKnownNeverNaN()
4845 case ISD::FDIV: in getNode()
5125 case ISD::FDIV: in getNode()
5161 case ISD::FDIV: in getNode()
7640 case ISD::STRICT_FDIV: NewOpc = ISD::FDIV; break; in mutateStrictFPToFP()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFPU.td | 37 defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,
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| H A D | MipsSEISelLowering.cpp | 135 setOperationAction(ISD::FDIV, MVT::f16, Promote); in MipsSETargetLowering()
383 setOperationAction(ISD::FDIV, Ty, Legal); in addMSAFloatType()
1828 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| H A D | MipsInstrFPU.td | 638 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>,
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| /freebsd-12.1/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1714 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1739 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1791 setOperationAction(ISD::FDIV, MVT::f32, Promote); in SparcTargetLowering()
3042 case ISD::FDIV: return LowerF128Op(Op, DAG, in LowerOperation()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 214 setOperationAction(ISD::FDIV, MVT::f128, Custom); in AArch64TargetLowering()
377 setOperationAction(ISD::FDIV, MVT::f16, Promote); in AArch64TargetLowering()
397 setOperationAction(ISD::FDIV, MVT::v4f16, Promote); in AArch64TargetLowering()
403 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32); in AArch64TargetLowering()
427 setOperationAction(ISD::FDIV, MVT::v8f16, Expand); in AArch64TargetLowering()
562 setTargetDAGCombine(ISD::FDIV); in AArch64TargetLowering()
628 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); in AArch64TargetLowering()
2894 case ISD::FDIV: in LowerOperation()
11199 case ISD::FDIV: in PerformDAGCombine()
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| H A D | AArch64SchedCyclone.td | 549 // FDIV,FSQRT
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| H A D | AArch64SchedA57.td | 457 // Note: These were simply duplicated from ASIMD FDIV because of missing documentation
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| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 226 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); in WebAssemblyTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1466 case FDiv: return ISD::FDIV; in InstructionOpcodeToISD()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 598 setOperationAction(ISD::FDIV, VT, Expand); in PPCTargetLowering()
673 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
729 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); in PPCTargetLowering()
835 setOperationAction(ISD::FDIV, MVT::f128, Legal); in PPCTargetLowering()
1018 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); in PPCTargetLowering()
1021 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
1024 setOperationAction(ISD::FDIV, MVT::v4f64, Expand); in PPCTargetLowering()
1027 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); in PPCTargetLowering()
1091 setTargetDAGCombine(ISD::FDIV); in PPCTargetLowering()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1377 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1421 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
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