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Searched refs:ElementWidth (Results 1 – 4 of 4) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp311 int ElementWidth; member
338 unsigned ElementWidth; member
1083 (ElementWidth == 0 || Reg.ElementWidth == ElementWidth)) in isSVEPredicateVectorRegOfWidth()
1095 (ElementWidth == 0 || Reg.ElementWidth == ElementWidth)) in isSVEDataVectorRegOfWidth()
1185 unsigned ElementWidth>
1193 if (VectorList.ElementWidth != ElementWidth) in isTypedVectorList()
1833 Op->Reg.ElementWidth = 0; in CreateReg()
1854 Op->Reg.ElementWidth = ElementWidth; in CreateVectorReg()
1866 Op->VectorList.ElementWidth = ElementWidth; in CreateVectorList()
3089 unsigned ElementWidth = KindRes->second; in tryParseNeonVectorRegister() local
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp217 template <int ElementWidth>
1837 template <int ElementWidth>
1842 if (ElementWidth == 8 && Shift) in DecodeImm8OptLsl()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td964 class ZPRVectorList<int ElementWidth, int NumRegs> : AsmOperandClass {
965 let Name = "SVEVectorList" # NumRegs # ElementWidth;
968 "isTypedVectorList<RegKind::SVEDataVector, " #NumRegs #", 0, " #ElementWidth #">";
H A DSVEInstrFormats.td151 class SVEShiftedImmOperand<int ElementWidth, string Infix, string Predicate>
153 let Name = "SVE" # Infix # "Imm" # ElementWidth;
170 class imm8_opt_lsl<int ElementWidth, string printType,
174 let DecoderMethod = "DecodeImm8OptLsl<" # ElementWidth # ">";