Lines Matching refs:ElementWidth
311 int ElementWidth; member
338 unsigned ElementWidth; member
1077 template <int ElementWidth, unsigned Class>
1083 (ElementWidth == 0 || Reg.ElementWidth == ElementWidth)) in isSVEPredicateVectorRegOfWidth()
1089 template <int ElementWidth, unsigned Class>
1095 (ElementWidth == 0 || Reg.ElementWidth == ElementWidth)) in isSVEDataVectorRegOfWidth()
1101 template <int ElementWidth, unsigned Class,
1105 auto VectorMatch = isSVEDataVectorRegOfWidth<ElementWidth, Class>(); in isSVEDataVectorRegWithShiftExtend()
1185 unsigned ElementWidth>
1193 if (VectorList.ElementWidth != ElementWidth) in isTypedVectorList()
1833 Op->Reg.ElementWidth = 0; in CreateReg()
1844 CreateVectorReg(unsigned RegNum, RegKind Kind, unsigned ElementWidth, in CreateVectorReg() argument
1854 Op->Reg.ElementWidth = ElementWidth; in CreateVectorReg()
1860 unsigned ElementWidth, RegKind RegisterKind, SMLoc S, SMLoc E, in CreateVectorList() argument
1866 Op->VectorList.ElementWidth = ElementWidth; in CreateVectorList()
3089 unsigned ElementWidth = KindRes->second; in tryParseNeonVectorRegister() local
3091 AArch64Operand::CreateVectorReg(Reg, RegKind::NeonVector, ElementWidth, in tryParseNeonVectorRegister()
3180 unsigned ElementWidth = KindRes->second; in tryParseSVEPredicateVector() local
3182 RegNum, RegKind::SVEPredicateVector, ElementWidth, S, in tryParseSVEPredicateVector()
3409 unsigned ElementWidth = 0; in tryParseVectorList() local
3412 std::tie(NumElements, ElementWidth) = *VK; in tryParseVectorList()
3416 FirstReg, Count, NumElements, ElementWidth, VectorKind, S, getLoc(), in tryParseVectorList()
5685 unsigned ElementWidth = KindRes->second; in tryParseSVEDataVector() local
5690 RegNum, RegKind::SVEDataVector, ElementWidth, S, S, getContext())); in tryParseSVEDataVector()
5709 RegNum, RegKind::SVEDataVector, ElementWidth, S, Ext->getEndLoc(), in tryParseSVEDataVector()