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Searched refs:EXTRACT_SUBVECTOR (Results 1 – 20 of 20) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1018 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
2703 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, in WidenVecRes_BinaryCanTrap()
2706 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, in WidenVecRes_BinaryCanTrap()
2793 ISD::EXTRACT_SUBVECTOR, dl, VT, Op, in WidenVecRes_StrictFP()
2902 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp, in WidenVecRes_Convert()
3369 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR) in isSETCCorConvertedSETCC()
3821 ISD::EXTRACT_SUBVECTOR, dl, VT, Res, in WidenVecOp_Convert()
3905 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), in WidenVecOp_EXTRACT_SUBVECTOR()
4057 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC, in WidenVecOp_SETCC()
4392 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp, in GenWidenVectorStores()
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H A DDAGCombiner.cpp1585 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
9921 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
14250 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in MergeStoresOfConstantsOrVecElts()
14419 Val.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
16092 !(VecIn2.getOpcode() == ISD::EXTRACT_SUBVECTOR) || in createBuildVecShuffle()
16527 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, in convertBuildVecZextToZext()
16689 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
16877 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
17148 ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, in visitEXTRACT_SUBVECTOR()
17959 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in visitINSERT_SUBVECTOR()
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H A DSelectionDAGDumper.cpp276 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
H A DLegalizeIntegerTypes.cpp94 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
332 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
852 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx); in PromoteIntRes_TRUNCATE()
1078 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break; in PromoteIntegerOperand()
3832 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1)); in PromoteIntOp_EXTRACT_SUBVECTOR()
H A DSelectionDAG.cpp2201 case ISD::EXTRACT_SUBVECTOR: { in isSplatValue()
2455 case ISD::EXTRACT_SUBVECTOR: { in computeKnownBits()
3682 case ISD::EXTRACT_SUBVECTOR: { in ComputeNumSignBits()
5029 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
5056 case ISD::EXTRACT_SUBVECTOR: in getNode()
9060 Lo = getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in SplitVector()
9062 Hi = getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, N, in SplitVector()
H A DSelectionDAGBuilder.cpp428 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, in getCopyFromPartsVector()
462 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, in getCopyFromPartsVector()
731 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, in getCopyToPartsVector()
3309 ISD::EXTRACT_SUBVECTOR, DL, VT, Result, in visitShuffleVector()
3355 ISD::EXTRACT_SUBVECTOR, DL, VT, Src, in visitShuffleVector()
H A DLegalizeDAG.cpp2894 case ISD::EXTRACT_SUBVECTOR: in ExpandNode()
H A DTargetLowering.cpp1638 case ISD::EXTRACT_SUBVECTOR: { in SimplifyDemandedVectorElts()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h358 EXTRACT_SUBVECTOR, enumerator
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp782 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForNEON()
2916 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
6394 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, in tryFormConcatFromShuffle()
6398 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1, in tryFormConcatFromShuffle()
6620 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in LowerVECTOR_SHUFFLE()
9407 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR && in performBitcastCombine()
9412 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) { in performBitcastCombine()
9624 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy, in tryExtendDUPToExtractHigh()
9630 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR) in isEssentiallyExtractSubvector()
10082 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src, in performExtendCombine()
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H A DAArch64ISelDAGToDAG.cpp479 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR) in checkHighLaneIndex()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp712 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1858 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR); in X86TargetLowering()
5691 while (V.getOpcode() == ISD::EXTRACT_SUBVECTOR) in peekThroughEXTRACT_SUBVECTORs()
5918 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getTargetConstantBitsFromNode()
6218 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getTargetShuffleMask()
18427 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, in LowerTRUNCATE()
20271 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, V, in LowerSIGN_EXTEND_Mask()
20551 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RegVT, in LowerLoad()
33231 N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) && in combineBitcast()
41246 if (SubVec.getOpcode() == ISD::EXTRACT_SUBVECTOR && in combineInsertSubvector()
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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp100 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
191 setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
1557 case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1432 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1476 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
2764 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp334 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
335 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
336 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
337 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
338 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
339 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
1147 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
H A DSIISelLowering.cpp262 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
508 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
7820 case ISD::EXTRACT_SUBVECTOR: { in isCanonicalized()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp178 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
5118 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
7524 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
7526 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
7528 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
7530 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
7560 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
7562 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
7564 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
7566 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
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/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td549 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
554 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2085 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp900 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand); in PPCTargetLowering()
949 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand); in PPCTargetLowering()
990 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand); in PPCTargetLowering()