| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 623 Register DefR(MD); in visitPHI() local
629 if (DefR.SubReg) { in visitPHI()
635 visitUsesOf(DefR.Reg); in visitPHI()
671 visitUsesOf(DefR.Reg); in visitPHI()
693 Register DefR(MO); in visitNonBranch() local
713 visitUsesOf(DefR.Reg); in visitNonBranch()
1925 Register DefR(MD); in evaluate() local
1926 assert(!DefR.SubReg); in evaluate()
2745 Outputs.update(DefR.Reg, RC); in evaluateHexExt()
2774 Outputs.update(DefR.Reg, RC); in evaluateHexVector1()
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| H A D | HexagonGenMux.cpp | 109 unsigned DefR, PredR; member
116 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
338 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) in genMuxInBlock()
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| H A D | HexagonConstExtenders.cpp | 1528 unsigned DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in insertInitializer() local
1542 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR) in insertInitializer()
1549 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR) in insertInitializer()
1554 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR) in insertInitializer()
1559 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR) in insertInitializer()
1567 InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR) in insertInitializer()
1579 return { DefR, 0 }; in insertInitializer()
1905 Register DefR = insertInitializer(Q.first, P.first); in replaceExtenders() local
1906 NewRegs.push_back(DefR.Reg); in replaceExtenders()
1908 Changed |= replaceInstr(I, DefR, P.first); in replaceExtenders()
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| H A D | HexagonEarlyIfConv.cpp | 441 unsigned DefR = MI.getOperand(0).getReg(); in isValid() local
442 if (isPredicate(DefR)) in isValid()
993 unsigned DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
1000 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in eliminatePhis()
1005 MRI->replaceRegWith(DefR, NewR); in eliminatePhis()
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| H A D | HexagonBitSimplify.cpp | 1224 unsigned DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local
1225 if (!TargetRegisterInfo::isVirtualRegister(DefR)) in computeUsedBits()
1227 Pending.push_back(DefR); in computeUsedBits()
2922 unsigned DefR; member
2929 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2948 DefR = HexagonLoopRescheduling::getDefReg(&P); in PhiInfo()
2983 unsigned DefR) const { in isBitShuffle()
3137 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" in processLoop()
3165 unsigned DefR = Defs.find_first(); in processLoop() local
3166 if (!TargetRegisterInfo::isVirtualRegister(DefR)) in processLoop()
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| H A D | HexagonOptAddrMode.cpp | 97 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
728 unsigned DefR = MI->getOperand(0).getReg(); in processBlock() local
733 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc)) in processBlock()
757 if (op.isReg() && op.isUse() && DefR == op.getReg()) in processBlock()
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| H A D | HexagonBitTracker.cpp | 964 if (unsigned DefR = getUniqueDefVReg(MI)) { in evaluate() local
965 if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) { in evaluate()
966 BT::RegisterRef PD(DefR, 0); in evaluate()
969 RegisterCell RC = RegisterCell::self(DefR, RW); in evaluate()
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