Searched refs:DefOp (Results 1 – 8 of 8) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | MachineTraceMetrics.cpp | 629 unsigned DefOp; member
632 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
642 DefOp = DefI.getOperandNo(); in DataDep()
742 for (unsigned DefOp : LiveDefOps) { in updatePhysDepsDownwards() local
747 LRU.Op = DefOp; in updatePhysDepsDownwards()
805 .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp); in updateDepth()
979 addLiveIns(const MachineInstr *DefMI, unsigned DefOp, in addLiveIns() argument
982 unsigned Reg = DefMI->getOperand(DefOp).getReg(); in addLiveIns()
1086 addLiveIns(Deps.front().DefMI, Deps.front().DefOp, Stack); in computeInstrHeights()
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| H A D | PeepholeOptimizer.cpp | 1523 MachineOperand &DefOp = MI.getOperand(0); in findTargetRecurrence() local
1524 if (!isVirtualRegisterOperand(DefOp)) in findTargetRecurrence()
1536 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC); in findTargetRecurrence()
1542 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC); in findTargetRecurrence()
1835 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast() local
1836 if (DefOp.getSubReg() != DefSubReg) in getNextSourceFromBitcast()
1859 for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) { in getNextSourceFromBitcast()
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| H A D | SplitKit.cpp | 440 for (const MachineOperand &DefOp : DefMI->defs()) { in addDeadDef() local
441 unsigned R = DefOp.getReg(); in addDeadDef()
444 if (unsigned SR = DefOp.getSubReg()) in addDeadDef()
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| H A D | MachinePipeliner.cpp | 257 MachineOperand &DefOp = PI.getOperand(0); in preprocessPhiNodes() local
258 assert(DefOp.getSubReg() == 0); in preprocessPhiNodes()
259 auto *RC = MRI.getRegClass(DefOp.getReg()); in preprocessPhiNodes()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 224 void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
854 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp, in predicateAt() argument
885 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86DomainReassignment.cpp | 594 for (auto &DefOp : UseMI.defs()) { in buildClosure() local
595 if (!DefOp.isReg()) in buildClosure()
598 unsigned DefReg = DefOp.getReg(); in buildClosure()
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| H A D | X86SpeculativeLoadHardening.cpp | 1595 if (MachineOperand *DefOp = MI.findRegisterDefOperand(X86::EFLAGS)) { in isEFLAGSLive() local
1597 if (DefOp->isDead()) in isEFLAGSLive()
2325 auto &DefOp = MI.getOperand(0); in hardenPostLoad() local
2326 unsigned OldDefReg = DefOp.getReg(); in hardenPostLoad()
2333 DefOp.setReg(UnhardenedReg); in hardenPostLoad()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineTraceMetrics.h | 336 void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
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