| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | LiveRangeShrink.cpp | 166 const MachineOperand *DefMO = nullptr; in runOnMachineFunction() local
187 if (DefMO) { in runOnMachineFunction()
191 DefMO = &MO; in runOnMachineFunction()
192 } else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg) && DefMO && in runOnMachineFunction()
193 MRI.getRegClass(DefMO->getReg()) == in runOnMachineFunction()
218 if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) { in runOnMachineFunction()
|
| H A D | MachineLICM.cpp | 1132 MachineOperand &DefMO = MI.getOperand(i); in IsCheapInstruction() local
1133 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
1136 unsigned Reg = DefMO.getReg(); in IsCheapInstruction()
|
| H A D | MachineInstr.cpp | 1037 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands() local
1039 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands()
1041 assert(!DefMO.isTied() && "Def is already tied to another use"); in tieOperands()
1055 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); in tieOperands()
|
| H A D | RegisterCoalescer.cpp | 1262 MachineOperand &DefMO = NewMI.getOperand(0); in reMaterializeTrivialDef() local
1263 if (DefMO.getSubReg() == DstIdx) { in reMaterializeTrivialDef()
1272 DefMO.setSubReg(0); in reMaterializeTrivialDef()
1273 DefMO.setIsUndef(false); // Only subregs can have def+undef. in reMaterializeTrivialDef()
|
| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyExplicitLocals.cpp | 177 for (MachineOperand &DefMO : Def->explicit_uses()) { in findStartOfTree()
178 if (!DefMO.isReg()) in findStartOfTree()
180 return findStartOfTree(DefMO, MRI, MFI); in findStartOfTree()
|
| H A D | WebAssemblyRegStackify.cpp | 601 MachineOperand &DefMO = Def->getOperand(0); in MoveAndTeeForMultiUse() local
605 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in MoveAndTeeForMultiUse()
607 DefMO.setReg(DefReg); in MoveAndTeeForMultiUse()
|
| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIInsertWaitcnts.cpp | 610 MachineOperand &DefMO = Inst.getOperand(I); in updateByEvent() local
611 if (DefMO.isReg() && DefMO.isDef() && in updateByEvent()
612 TRI->isVGPR(MRIA, DefMO.getReg())) { in updateByEvent()
613 setRegScore(TRI->getEncodingValue(DefMO.getReg()), EXP_CNT, in updateByEvent()
|
| H A D | SIPeepholeSDWA.cpp | 326 for (auto &DefMO : DefInstr->defs()) { in findSingleRegDef() local
327 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
328 return &DefMO; in findSingleRegDef()
|
| H A D | SIInstrInfo.h | 641 const MachineOperand &DefMO) const { in isInlineConstant() argument
648 return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]); in isInlineConstant()
|
| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 372 const MachineOperand &DefMO, unsigned Reg,
|
| H A D | ARMBaseInstrInfo.cpp | 4053 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4054 unsigned Reg = DefMO.getReg(); in getOperandLatency()
4076 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO, in getOperandLatency()
4083 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, in getOperandLatencyImpl() argument
4111 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit()) in getOperandLatencyImpl()
|
| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 4058 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4060 if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.getReg())) { in getOperandLatency()
4061 if (DefMO.isImplicit()) { in getOperandLatency()
4062 for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) { in getOperandLatency()
|
| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 187 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
188 unsigned Reg = DefMO.getReg(); in getOperandLatency()
|