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Searched refs:DefInst (Results 1 – 8 of 8) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFixupVectorISel.cpp98 MachineInstr *DefInst = MRI.getUniqueVRegDef(WOp->getReg()); in findSRegBaseAndIndex() local
99 switch (DefInst->getOpcode()) { in findSRegBaseAndIndex()
103 Worklist.push_back(&DefInst->getOperand(1)); in findSRegBaseAndIndex()
106 if (DefInst->getNumOperands() != 5) in findSRegBaseAndIndex()
108 Worklist.push_back(&DefInst->getOperand(1)); in findSRegBaseAndIndex()
109 Worklist.push_back(&DefInst->getOperand(3)); in findSRegBaseAndIndex()
115 if (DefInst->getOperand(2).getSubReg() != AMDGPU::NoSubRegister) in findSRegBaseAndIndex()
117 BaseReg = DefInst->getOperand(2).getReg(); in findSRegBaseAndIndex()
118 if (DefInst->getOperand(3).getSubReg() != AMDGPU::NoSubRegister) in findSRegBaseAndIndex()
120 IndexReg = DefInst->getOperand(3).getReg(); in findSRegBaseAndIndex()
H A DSIPeepholeSDWA.cpp531 const MachineInstr *DefInst = Def.getParent(); in foldToImm() local
532 if (!TII->isFoldableCopy(*DefInst)) in foldToImm()
535 const MachineOperand &Copied = DefInst->getOperand(1); in foldToImm()
H A DSIInstrInfo.cpp5613 auto *DefInst = MRI.getVRegDef(RSR.Reg); in getVRegSubRegDef() local
5614 while (auto *MI = DefInst) { in getVRegSubRegDef()
5615 DefInst = nullptr; in getVRegSubRegDef()
5625 DefInst = MRI.getVRegDef(RSR.Reg); in getVRegSubRegDef()
5633 DefInst = MRI.getVRegDef(RSR.Reg); in getVRegSubRegDef()
5636 if (!DefInst) in getVRegSubRegDef()
/freebsd-12.1/contrib/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp369 Instruction *DefInst = nullptr; member
377 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId), in LoadValue()
983 if (InVal.DefInst != nullptr && in processNode()
991 InVal.DefInst, Inst))) { in processNode()
992 Value *Op = getOrCreateResult(InVal.DefInst, Inst->getType()); in processNode()
995 << " to: " << *InVal.DefInst << '\n'); in processNode()
1076 if (InVal.DefInst && in processNode()
1077 InVal.DefInst == getOrCreateResult(Inst, InVal.DefInst->getType()) && in processNode()
1083 InVal.DefInst, Inst))) { in processNode()
H A DNewGVN.cpp3970 auto *DefInst = dyn_cast_or_null<Instruction>(Def); in eliminateInstructions() local
3971 if (DefInst && AllTempInstructions.count(DefInst)) { in eliminateInstructions()
3972 auto *PN = cast<PHINode>(DefInst); in eliminateInstructions()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp415 MachineInstr *DefInst = LastDef[Reg]; in findPotentialNewifiableTFRs() local
416 if (!DefInst) in findPotentialNewifiableTFRs()
418 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively)) in findPotentialNewifiableTFRs()
423 MachineBasicBlock::iterator It(DefInst); in findPotentialNewifiableTFRs()
434 PotentiallyNewifiableTFR.insert(DefInst); in findPotentialNewifiableTFRs()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp465 MachineInstr *DefInst = MRI->getVRegDef(Use.getReg()); in canMoveToEnd() local
466 if (DefInst->isPHI() && DefInst->getParent() == MI.getParent()) { in canMoveToEnd()
/freebsd-12.1/contrib/llvm/lib/Analysis/
H A DMemorySSA.cpp259 Instruction *DefInst = MD->getMemoryInst(); in instructionClobbersQuery() local
260 assert(DefInst && "Defining instruction not actually an instruction"); in instructionClobbersQuery()
264 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(DefInst)) { in instructionClobbersQuery()
289 ModRefInfo I = AA.getModRefInfo(DefInst, UseCall); in instructionClobbersQuery()
294 if (auto *DefLoad = dyn_cast<LoadInst>(DefInst)) in instructionClobbersQuery()
298 ModRefInfo I = AA.getModRefInfo(DefInst, UseLoc); in instructionClobbersQuery()