| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenPredicate.cpp | 232 DefI->eraseFromParent(); in processPredicateGPR()
254 assert(DefI); in getPredRegFor()
255 unsigned Opc = DefI->getOpcode(); in getPredRegFor()
257 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
258 Register PR = DefI->getOperand(1); in getPredRegFor()
264 MachineBasicBlock &B = *DefI->getParent(); in getPredRegFor()
265 DebugLoc DL = DefI->getDebugLoc(); in getPredRegFor()
271 if (isConvertibleToPredForm(DefI)) { in getPredRegFor()
272 MachineBasicBlock::iterator DefIt = DefI; in getPredRegFor()
328 if (!DefI) in isScalarPred()
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| H A D | HexagonExpandCondsets.cpp | 343 if (HII->isPredicated(*DefI)) in updateKillFlags()
420 Defs.insert(DefI->getParent()); in updateDeadsInRange()
421 if (HII->isPredicated(*DefI)) in updateDeadsInRange()
474 for (auto &Op : DefI->operands()) { in updateDeadsInRange()
491 if (!HII->isPredicated(*DefI)) in updateDeadsInRange()
498 MachineOperand &Op = DefI->getOperand(i); in updateDeadsInRange()
522 DefI->tieOperands(P.second, DefI->getNumOperands()-1); in updateDeadsInRange()
960 if (!DefI || !isPredicable(DefI)) in predicate()
1044 if (DefI->mayLoad() || DefI->mayStore()) in predicate()
1045 if (!canMoveMemTo(*DefI, TfrI, true)) in predicate()
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| H A D | HexagonVExtract.cpp | 128 MachineInstr *DefI = MRI.getVRegDef(VecR); in runOnMachineFunction() local
129 MachineBasicBlock::iterator At = std::next(DefI->getIterator()); in runOnMachineFunction()
130 MachineBasicBlock &DefB = *DefI->getParent(); in runOnMachineFunction()
134 BuildMI(DefB, At, DefI->getDebugLoc(), HII->get(StoreOpc)) in runOnMachineFunction()
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| H A D | HexagonSplitDouble.cpp | 236 MachineInstr *DefI = MRI->getVRegDef(R); in partitionRegisters() local
240 if (!DefI || isFixedInstr(DefI)) in partitionRegisters()
406 const MachineInstr *DefI = MRI->getVRegDef(Reg); in profit() local
407 switch (DefI->getOpcode()) { in profit()
415 return profit(DefI); in profit()
428 MachineInstr *DefI = MRI->getVRegDef(DR); in isProfitable() local
429 int32_t P = profit(DefI); in isProfitable()
1140 MachineInstr *DefI = MRI->getVRegDef(DR); in splitPartition() local
1141 SplitIns.insert(DefI); in splitPartition()
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| H A D | HexagonGenInsert.cpp | 1021 const MachineInstr *DefI = MRI->getVRegDef(R); in findRemovableRegisters() local
1022 assert(DefI); in findRemovableRegisters()
1026 if (DefI->isPHI()) in findRemovableRegisters()
1028 getInstrUses(DefI, Regs[OtherS]); in findRemovableRegisters()
1159 const MachineInstr *DefI = MRI->getVRegDef(IR); in pruneUsesTooFar() local
1162 unsigned DIV = distance(DefI, DefV, RPO, M); in pruneUsesTooFar()
1347 const MachineInstr *DefI = MRI->getVRegDef(I->first); in selectCandidates() local
1348 getInstrUses(DefI, Us); in selectCandidates()
1445 MachineInstr *DefI = MRI->getVRegDef(I->first); in generateInserts() local
1447 DefI->eraseFromParent(); in generateInserts()
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| H A D | HexagonEarlyIfConv.cpp | 408 const MachineInstr *DefI = MRI->getVRegDef(R); in usesUndefVReg() local
410 assert(DefI && "Expecting a reaching def in MRI"); in usesUndefVReg()
411 if (DefI->isImplicitDef()) in usesUndefVReg()
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| H A D | HexagonConstExtenders.cpp | 1504 const MachineInstr *DefI = Rs.isVReg() ? MRI->getVRegDef(Rs.Reg) : nullptr; in calculatePlacement() local
1508 assert(!DefI || MDT->dominates(DefI->getParent(), DomB)); in calculatePlacement()
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| H A D | HexagonBitSimplify.cpp | 2291 MachineInstr *DefI = MRI.getVRegDef(Op0.getReg()); in genBitSplit() local
2292 assert(DefI != nullptr); in genBitSplit()
2293 if (!MDT.dominates(DefI, &*At)) in genBitSplit()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | MIRCanonicalizerPass.cpp | 261 MachineBasicBlock::iterator DefI = BBE; in rescheduleCanonically() local
266 if (DefI != BBE && UseI != BBE) in rescheduleCanonically()
270 DefI = BBI; in rescheduleCanonically()
280 if (DefI == BBE || UseI == BBE) in rescheduleCanonically()
285 DefI->dump(); in rescheduleCanonically()
292 MBB->splice(UseI, MBB, DefI); in rescheduleCanonically()
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| H A D | MachineTraceMetrics.cpp | 639 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg); in DataDep() local
640 assert(!DefI.atEnd() && "Register has no defs"); in DataDep()
641 DefMI = DefI->getParent(); in DataDep()
642 DefOp = DefI.getOperandNo(); in DataDep()
643 assert((++DefI).atEnd() && "Register has multiple defs"); in DataDep()
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| /freebsd-12.1/contrib/llvm/include/llvm/Analysis/ |
| H A D | LoopInfo.h | 908 auto *DefI = dyn_cast<Instruction>(U.get()); in movementPreservesLCSSAForm() local
909 if (!DefI) in movementPreservesLCSSAForm()
915 auto *DefBlock = DefI->getParent(); in movementPreservesLCSSAForm()
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| /freebsd-12.1/contrib/llvm/lib/Transforms/Scalar/ |
| H A D | IndVarSimplify.cpp | 246 auto *DefI = dyn_cast<Instruction>(Def); in getInsertPointForUses() local
247 if (!DefI) in getInsertPointForUses()
250 assert(DT->dominates(DefI, InsertPt) && "def does not dominate all uses"); in getInsertPointForUses()
252 auto *L = LI->getLoopFor(DefI->getParent()); in getInsertPointForUses()
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| /freebsd-12.1/contrib/llvm/tools/clang/utils/TableGen/ |
| H A D | NeonEmitter.cpp | 1514 DefInit *DefI = cast<DefInit>(DI->getOperator()); in emitDag() local
1515 std::string Op = DefI->getAsString(); in emitDag()
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