| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | MachineTraceMetrics.cpp | 793 unsigned Cycle = 0; in updateDepth() local
806 Cycle = std::max(Cycle, DepCycle); in updateDepth()
810 MICycles.Depth = Cycle; in updateDepth()
919 unsigned DepHeight = I->Cycle; in updatePhysDepsUpwards()
939 LRU.Cycle = Height; in updatePhysDepsUpwards()
1038 RegUnits[LI.Reg].Cycle = LI.Height; in computeInstrHeights()
1098 unsigned Cycle = 0; in computeInstrHeights() local
1101 Cycle = HeightI->second; in computeInstrHeights()
1113 Cycle = updatePhysDepsUpwards(MI, Cycle, RegUnits, MTM.SchedModel, in computeInstrHeights()
1122 MICycles.Height = Cycle; in computeInstrHeights()
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| H A D | MachinePipeliner.cpp | 1856 for (int Cycle = Schedule.getFirstCycle(), in generatePipelinedLoop() local
1858 Cycle <= LastCycle; ++Cycle) { in generatePipelinedLoop()
1859 std::deque<SUnit *> &CycleInstrs = Schedule.getInstructions(Cycle); in generatePipelinedLoop()
3690 for (int Cycle = getFirstCycle(), E = getFinalCycle(); Cycle <= E; ++Cycle) { in finalizeSchedule() local
3691 std::deque<SUnit *> &cycleInstrs = ScheduledInstrs[Cycle]; in finalizeSchedule()
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| H A D | IfConversion.cpp | 283 unsigned Cycle, unsigned Extra, in MeetIfcvtSizeLimit() argument
285 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra, in MeetIfcvtSizeLimit()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 705 // 6 Cycle Load uses a single slice.
1122 // 33 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1129 // 36 Cycle DP Instruction.
1142 // 36 Cycle DP Vector Instruction.
1149 // 27 Cycle DP Vector Instruction.
1156 // 36 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1163 // 26 Cycle DP Instruction.
1175 // 26 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1194 // 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
1284 // Two Cycle Branch
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| H A D | PPCInstrInfo.cpp | 167 int Cycle = ItinData->getOperandCycle(DefClass, i); in getInstrLatency() local
168 if (Cycle < 0) in getInstrLatency()
171 Latency = std::max(Latency, (unsigned) Cycle); in getInstrLatency()
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| /freebsd-12.1/contrib/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 273 bool contains(unsigned Cycle) const { return Cycle >= Begin && Cycle < End; } in contains() argument
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 1113 ValueSeq &Cycle) { in findCycle() argument
1134 if (Cycle.count(I)) in findCycle()
1136 Cycle.insert(I); in findCycle()
1139 Cycle.remove(I); in findCycle()
1141 return !Cycle.empty(); in findCycle()
1151 unsigned I, N = Cycle.size(); in classifyCycle()
1153 Value *V = Cycle[I]; in classifyCycle()
1165 First.insert(Cycle[J]); in classifyCycle()
1168 Second.insert(Cycle[I]); in classifyCycle()
1170 Value *V = Cycle[I]; in classifyCycle()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 463 unsigned Cycle = getTransSwizzle(TransSwz, i); in isLegalUpTo() local
468 if (Vector[Src.second][Cycle] < 0) in isLegalUpTo()
469 Vector[Src.second][Cycle] = Src.first; in isLegalUpTo()
470 if (Vector[Src.second][Cycle] != Src.first) in isLegalUpTo()
524 unsigned Cycle = getTransSwizzle(TransSwz, i); in isConstCompatible() local
527 if (ConstCount > 0 && Cycle == 0) in isConstCompatible()
529 if (ConstCount > 1 && Cycle == 1) in isConstCompatible()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAG.h | 550 void setCurCycle(unsigned Cycle) {
551 CurCycle = Cycle;
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| H A D | MachineTraceMetrics.h | 78 unsigned Cycle = 0; member
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| /freebsd-12.1/contrib/gcc/config/arm/ |
| H A D | arm1136jfs.md | 245 ;; stat prediction. Cycle count ranges from zero (unconditional branch,
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| /freebsd-12.1/contrib/processor-trace/libipt/include/ |
| H A D | intel-pt.h.in | 271 * multi-byte CYC (Cycle Count) packet, instead of any remaining bytes
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| /freebsd-12.1/contrib/llvm/tools/clang/include/clang/Basic/ |
| H A D | DiagnosticSemaKinds.td | 3061 "Cycle in acquired_before/after dependencies, starting with '%0'">,
5332 let CategoryName = "ARC Retain Cycle" in {
5341 } // end "ARC Retain Cycle" category
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