| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 85 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
121 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
443 case ISD::CopyFromReg: in SUSchedulingCost()
547 case ISD::CopyFromReg: in initNumRegDefsLeft()
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| H A D | StatepointLowering.cpp | 343 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
950 SDValue CopyFromReg = getCopyFromRegs(I, RetTy); in visitGCResult() local
952 assert(CopyFromReg.getNode()); in visitGCResult()
953 setValue(&CI, CopyFromReg); in visitGCResult()
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| H A D | ScheduleDAGRRList.cpp | 318 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
706 case ISD::CopyFromReg: in EmitNode()
1268 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2254 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2345 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2416 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2433 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
2961 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
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| H A D | InstrEmitter.cpp | 362 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
962 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
1025 case ISD::CopyFromReg: { in EmitSpecialNode()
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| H A D | ScheduleDAGSDNodes.cpp | 123 if (Def->getOpcode() == ISD::CopyFromReg && in CheckForPhysRegDependency()
529 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
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| H A D | ScheduleDAGFast.cpp | 429 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
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| H A D | SelectionDAGDumper.cpp | 169 case ISD::CopyFromReg: return "CopyFromReg"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 63 case ISD::CopyFromReg: in SoftenFloatResult()
805 case ISD::CopyFromReg: in CanSkipSoftenFloatOperand()
818 case ISD::CopyFromReg: // Operand is a register that we know to be left in CanSkipSoftenFloatOperand()
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| H A D | SelectionDAGBuilder.cpp | 4933 case ISD::CopyFromReg: in getUnderlyingArgReg()
8236 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg)) in visitPatchpoint()
8780 assert((Op.getOpcode() != ISD::CopyFromReg || in CopyValueToVirtualRegister()
9265 if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) { in LowerArguments()
9274 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { in LowerArguments()
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| H A D | SelectionDAGISel.cpp | 2959 case ISD::CopyFromReg: in SelectCodeCommon()
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| H A D | TargetLowering.cpp | 92 if (Value->getOpcode() != ISD::CopyFromReg) in parametersInCSRMatch()
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| H A D | DAGCombiner.cpp | 1806 case ISD::CopyFromReg: in visitTokenFactor()
6353 bool isCopyOrSelect = BinOpLHSVal->getOpcode() == ISD::CopyFromReg || in visitShiftByConstant()
19206 case ISD::CopyFromReg: in GatherAllAliases()
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| /freebsd-12.1/contrib/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 251 if (CopyFromRegOp->getOpcode() == ISD::CopyFromReg) { in SelectInlineAsmMemoryOperand()
301 SDValue CopyFromReg = in SelectInlineAsmMemoryOperand() local
304 OutOps.push_back(CopyFromReg); in SelectInlineAsmMemoryOperand()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 175 CopyFromReg, enumerator
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| H A D | SelectionDAG.h | 708 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
718 return getNode(ISD::CopyFromReg, dl, VTs,
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| /freebsd-12.1/contrib/llvm/lib/Target/BPF/ |
| H A D | BPFISelDAGToDAG.cpp | 560 if (BaseV.getOpcode() != ISD::CopyFromReg) in PreprocessTrunc()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 233 Opc != ISD::CopyFromReg; in isDef32()
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| /freebsd-12.1/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 389 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
395 N->getOpcode() != ISD::CopyFromReg;
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrCompiler.td | 1338 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1341 // 32 bits, they're probably just qualifying a CopyFromReg.
1345 N->getOpcode() != ISD::CopyFromReg &&
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| H A D | X86ISelDAGToDAG.cpp | 356 if (OtherOp->getOpcode() == ISD::CopyFromReg && in shouldAvoidImmediateInstFormsForSize()
1738 RHS.getNode()->getOpcode() == ISD::CopyFromReg || in matchAddressRecursively()
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| H A D | X86ISelLowering.cpp | 4237 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
20198 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){ in LowerSELECT()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 9591 assert(N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
9597 } while (N->getOpcode() == ISD::CopyFromReg); in isCopyFromRegOfInlineAsm()
9605 case ISD::CopyFromReg: in isSDNodeSourceOfDivergence()
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| /freebsd-12.1/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1310 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 2249 if (Arg.getOpcode() == ISD::CopyFromReg) { in MatchingStackOffset()
5146 if (Op.getOpcode() != ISD::CopyFromReg || in ExpandBITCAST()
5155 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops); in ExpandBITCAST()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4170 return AddrOp.getOpcode() == ISD::CopyFromReg; in isOffsetMultipleOf()
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