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/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFSubtarget.cpp29 BPFSubtarget &BPFSubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
32 initSubtargetFeatures(CPU, FS); in initializeSubtargetDependencies()
33 ParseSubtargetFeatures(CPU, FS); in initializeSubtargetDependencies()
43 void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { in initSubtargetFeatures() argument
44 if (CPU == "probe") in initSubtargetFeatures()
45 CPU = sys::detail::getHostCPUNameForBPF(); in initSubtargetFeatures()
46 if (CPU == "generic" || CPU == "v1") in initSubtargetFeatures()
48 if (CPU == "v2") { in initSubtargetFeatures()
54 BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU, in BPFSubtarget() argument
56 : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), in BPFSubtarget()
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/freebsd-12.1/contrib/llvm/lib/MC/
H A DMCSubtargetInfo.cpp23 static FeatureBitset getFeatures(StringRef CPU, StringRef FS, in getFeatures() argument
27 return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures); in getFeatures()
31 FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures); in InitMCProcessorInfo()
32 if (!CPU.empty()) in InitMCProcessorInfo()
33 CPUSchedModel = &getSchedModelForCPU(CPU); in InitMCProcessorInfo()
39 FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures); in setDefaultFeatures()
48 : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD), in MCSubtargetInfo()
51 InitMCProcessorInfo(CPU, FS); in MCSubtargetInfo()
102 errs() << "'" << CPU in getSchedModelForCPU()
112 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const { in getInstrItineraryForCPU()
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/freebsd-12.1/contrib/llvm/lib/Support/
H A DAArch64TargetParser.cpp29 if (CPU == "generic") in getDefaultFPU()
32 return StringSwitch<unsigned>(CPU) in getDefaultFPU()
40 if (CPU == "generic") in getDefaultExtensions()
43 return StringSwitch<unsigned>(CPU) in getDefaultExtensions()
52 AArch64::ArchKind AArch64::getCPUArchKind(StringRef CPU) { in getCPUArchKind() argument
53 if (CPU == "generic") in getCPUArchKind()
56 return StringSwitch<AArch64::ArchKind>(CPU) in getCPUArchKind()
158 for (const auto &CPU : AArch64CPUNames) in getDefaultCPU() local
159 if (CPU.ArchID == AK && CPU.Default) in getDefaultCPU()
160 return CPU.getName(); in getDefaultCPU()
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/freebsd-12.1/contrib/compiler-rt/lib/xray/
H A Dxray_fdr_controller.h149 if (UNLIKELY(LatestCPU != CPU || LatestTSC == 0)) { in recordPreamble()
153 LatestCPU = CPU; in recordPreamble()
162 DCHECK_EQ(LatestCPU, CPU); in recordPreamble()
183 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in rewindRecords() argument
246 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in functionEnter() argument
251 auto PreambleStatus = recordPreamble(TSC, CPU); in functionEnter()
277 auto PreambleStatus = recordPreamble(TSC, CPU); in functionTailExit()
284 return rewindRecords(FuncId, TSC, CPU); in functionTailExit()
312 uint16_t CPU) XRAY_NEVER_INSTRUMENT { in functionExit() argument
317 auto PreambleStatus = recordPreamble(TSC, CPU); in functionExit()
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H A Dxray_fdr_logging.cc414 unsigned char CPU = 0; member
430 Result.TSC = __xray::readTSC(Result.CPU); in getTimestamp()
439 Result.CPU = 0; in getTimestamp()
500 auto &CPU = TC.CPU; in fdrLoggingHandleArg0() local
512 TLD.Controller->functionEnter(FuncId, TSC, CPU); in fdrLoggingHandleArg0()
515 TLD.Controller->functionExit(FuncId, TSC, CPU); in fdrLoggingHandleArg0()
518 TLD.Controller->functionTailExit(FuncId, TSC, CPU); in fdrLoggingHandleArg0()
530 auto &CPU = TC.CPU; in fdrLoggingHandleArg1() local
545 TLD.Controller->functionExit(FuncId, TSC, CPU); in fdrLoggingHandleArg1()
560 auto &CPU = TC.CPU; in fdrLoggingHandleCustomEvent() local
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/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZTargetMachine.cpp38 static bool UsesVectorABI(StringRef CPU, StringRef FS) { in UsesVectorABI() argument
43 if (CPU.empty() || CPU == "generic" || in UsesVectorABI()
44 CPU == "z10" || CPU == "z196" || CPU == "zEC12") in UsesVectorABI()
59 static std::string computeDataLayout(const Triple &TT, StringRef CPU, in computeDataLayout() argument
61 bool VectorABI = UsesVectorABI(CPU, FS); in computeDataLayout()
147 StringRef CPU, StringRef FS, in SystemZTargetMachine() argument
153 T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, in SystemZTargetMachine()
158 Subtarget(TT, CPU, FS, *this) { in SystemZTargetMachine()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.cpp48 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { in selectMipsCPU() argument
49 if (CPU.empty() || CPU == "generic") { in selectMipsCPU()
52 CPU = "mips32r6"; in selectMipsCPU()
54 CPU = "mips64r6"; in selectMipsCPU()
57 CPU = "mips32"; in selectMipsCPU()
59 CPU = "mips64"; in selectMipsCPU()
62 return CPU; in selectMipsCPU()
78 StringRef CPU, StringRef FS) { in createMipsMCSubtargetInfo() argument
79 CPU = MIPS_MC::selectMipsCPU(TT, CPU); in createMipsMCSubtargetInfo()
80 return createMipsMCSubtargetInfoImpl(TT, CPU, FS); in createMipsMCSubtargetInfo()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsTargetMachine.cpp62 static std::string computeDataLayout(const Triple &TT, StringRef CPU, in computeDataLayout() argument
111 StringRef CPU, StringRef FS, in MipsTargetMachine() argument
118 CPU, FS, Options, getEffectiveRelocModel(JIT, RM), in MipsTargetMachine()
121 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), in MipsTargetMachine()
122 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, in MipsTargetMachine()
137 StringRef CPU, StringRef FS, in MipsebTargetMachine() argument
142 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} in MipsebTargetMachine()
147 StringRef CPU, StringRef FS, in MipselTargetMachine() argument
152 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} in MipselTargetMachine()
159 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) in getSubtargetImpl() local
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/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h38 std::string CPU; // CPU being targeted. variable
56 MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
69 StringRef getCPU() const { return CPU; } in getCPU()
85 void InitMCProcessorInfo(StringRef CPU, StringRef FS);
90 void setDefaultFeatures(StringRef CPU, StringRef FS);
113 const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
157 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
170 bool isCPUStringValid(StringRef CPU) const { in isCPUStringValid() argument
171 auto Found = std::lower_bound(ProcDesc.begin(), ProcDesc.end(), CPU); in isCPUStringValid()
172 return Found != ProcDesc.end() && StringRef(Found->Key) == CPU; in isCPUStringValid()
/freebsd-12.1/contrib/llvm/tools/clang/lib/Driver/ToolChains/Arch/
H A DX86.cpp34 std::string CPU = llvm::sys::getHostCPUName(); in getX86TargetCPU() local
35 if (!CPU.empty() && CPU != "generic") in getX86TargetCPU()
36 return Args.MakeArgString(CPU); in getX86TargetCPU()
42 const char *CPU = nullptr; in getX86TargetCPU() local
44 CPU = llvm::StringSwitch<const char *>(Arch) in getX86TargetCPU()
50 if (CPU == nullptr) { // 32-bit and 64-bit /arch: flags. in getX86TargetCPU()
51 CPU = llvm::StringSwitch<const char *>(Arch) in getX86TargetCPU()
58 if (CPU) { in getX86TargetCPU()
60 return CPU; in getX86TargetCPU()
H A DAArch64.cpp33 std::string CPU; in getAArch64TargetCPU() local
37 CPU = Mcpu.split("+").first.lower(); in getAArch64TargetCPU()
41 if (CPU == "native") in getAArch64TargetCPU()
43 else if (CPU.size()) in getAArch64TargetCPU()
44 return CPU; in getAArch64TargetCPU()
77 CPU = Split.first; in DecodeAArch64Mcpu()
79 if (CPU == "native") in DecodeAArch64Mcpu()
80 CPU = llvm::sys::getHostCPUName(); in DecodeAArch64Mcpu()
82 if (CPU == "generic") { in DecodeAArch64Mcpu()
120 StringRef CPU; in getAArch64ArchFeaturesFromMcpu() local
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/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcTargetMachine.cpp93 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, in SparcTargetMachine() argument
102 Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) { in SparcTargetMachine()
113 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) in getSubtargetImpl() local
130 auto &I = SubtargetMap[CPU + FS]; in getSubtargetImpl()
136 I = llvm::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this, in getSubtargetImpl()
193 StringRef CPU, StringRef FS, in SparcV8TargetMachine() argument
198 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} in SparcV8TargetMachine()
203 StringRef CPU, StringRef FS, in SparcV9TargetMachine() argument
208 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} in SparcV9TargetMachine()
213 StringRef CPU, StringRef FS, in SparcelTargetMachine() argument
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/freebsd-12.1/contrib/llvm/tools/clang/lib/Basic/Targets/
H A DMips.h45 std::string CPU; variable
79 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; in MipsTargetInfo()
86 return CPU == "mips32r6" || CPU == "mips64r6"; in isIEEE754_2008Default()
171 CPU = Name; in setCPU()
175 const std::string &getCPU() const { return CPU; } in getCPU()
178 StringRef CPU, in initFeatureMap() argument
180 if (CPU.empty()) in initFeatureMap()
181 CPU = getCPU(); in initFeatureMap()
182 if (CPU == "octeon") in initFeatureMap()
185 Features[CPU] = true; in initFeatureMap()
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H A DMips.cpp33 return llvm::StringSwitch<bool>(CPU) in processorSupportsGPR64()
190 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); in getTargetDefines()
191 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); in getTargetDefines()
222 Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU; in validateTarget()
228 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; in validateTarget()
234 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; in validateTarget()
265 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU; in validateTarget()
269 if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" || in validateTarget()
270 CPU == "mips64r6")) { in validateTarget()
271 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU; in validateTarget()
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H A DPPC.cpp119 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); in getTargetDefines()
253 Features["altivec"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
268 Features["qpx"] = (CPU == "a2q"); in initFeatureMap()
269 Features["power9-vector"] = (CPU == "pwr9"); in initFeatureMap()
270 Features["crypto"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
275 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
280 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
286 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
292 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
297 Features["vsx"] = llvm::StringSwitch<bool>(CPU) in initFeatureMap()
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H A DAMDGPU.cpp127 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, in initFeatureMap() argument
134 if (CPU.empty()) in initFeatureMap()
135 CPU = "gfx600"; in initFeatureMap()
137 switch (llvm::AMDGPU::parseArchAMDGCN(CPU)) { in initFeatureMap()
173 if (CPU.empty()) in initFeatureMap()
174 CPU = "r600"; in initFeatureMap()
176 switch (llvm::AMDGPU::parseArchR600(CPU)) { in initFeatureMap()
201 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); in initFeatureMap()
241 llvm::AMDGPU::parseArchAMDGCN(Opts.CPU) : in AMDGPUTargetInfo()
242 llvm::AMDGPU::parseArchR600(Opts.CPU)), in AMDGPUTargetInfo()
H A DHexagon.cpp28 if (CPU == "hexagonv5") { in getTargetDefines()
35 } else if (CPU == "hexagonv55") { in getTargetDefines()
40 } else if (CPU == "hexagonv60") { in getTargetDefines()
45 } else if (CPU == "hexagonv62") { in getTargetDefines()
48 } else if (CPU == "hexagonv65") { in getTargetDefines()
51 } else if (CPU == "hexagonv66") { in getTargetDefines()
72 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, in initFeatureMap() argument
76 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); in initFeatureMap()
H A DSystemZ.h29 std::string CPU; variable
36 : TargetInfo(Triple), CPU("z10"), ISARevision(8), in SystemZTargetInfo()
88 CPU = Name; in setCPU()
89 ISARevision = getISARevision(CPU); in setCPU()
95 StringRef CPU, in initFeatureMap() argument
97 int ISARevision = getISARevision(CPU); in initFeatureMap()
104 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); in initFeatureMap()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRSubtarget.cpp31 AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU, in AVRSubtarget() argument
33 : AVRGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(), in AVRSubtarget()
34 TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)), TSInfo(), in AVRSubtarget()
44 ParseSubtargetFeatures(CPU, FS); in AVRSubtarget()
48 AVRSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, in initializeSubtargetDependencies() argument
51 ParseSubtargetFeatures(CPU, FS); in initializeSubtargetDependencies()
H A DAVRTargetMachine.cpp31 static StringRef getCPU(StringRef CPU) { in getCPU() argument
32 if (CPU.empty() || CPU == "generic") { in getCPU()
36 return CPU; in getCPU()
44 StringRef CPU, StringRef FS, in AVRTargetMachine() argument
49 : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options, in AVRTargetMachine()
52 SubTarget(TT, getCPU(CPU), FS, *this) { in AVRTargetMachine()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXSubtarget.cpp34 NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
37 TargetName = CPU.empty() ? "sm_20" : CPU; in initializeSubtargetDependencies()
49 NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU, in NVPTXSubtarget() argument
52 : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM), in NVPTXSubtarget()
53 InstrInfo(), TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), in NVPTXSubtarget()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.cpp29 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
33 std::string CPUName = CPU; in initializeSubtargetDependencies()
44 RISCVSubtarget::RISCVSubtarget(const Triple &TT, const std::string &CPU, in RISCVSubtarget() argument
46 : RISCVGenSubtargetInfo(TT, CPU, FS), in RISCVSubtarget()
47 FrameLowering(initializeSubtargetDependencies(CPU, FS, TT.isArch64Bit())), in RISCVSubtarget()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMTargetMachine.cpp109 computeTargetABI(const Triple &TT, StringRef CPU, in computeTargetABI() argument
114 ABIName = ARM::computeDefaultTargetABI(TT, CPU); in computeTargetABI()
127 static std::string computeDataLayout(const Triple &TT, StringRef CPU, in computeDataLayout() argument
130 auto ABI = computeTargetABI(TT, CPU, Options); in computeDataLayout()
200 StringRef CPU, StringRef FS, in ARMBaseTargetMachine() argument
208 TargetABI(computeTargetABI(TT, CPU, Options)), in ARMBaseTargetMachine()
248 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) in getSubtargetImpl() local
267 auto &I = SubtargetMap[CPU + FS]; in getSubtargetImpl()
289 StringRef CPU, StringRef FS, in ARMLETargetMachine() argument
294 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in ARMLETargetMachine()
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/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCSubtarget.cpp43 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies() argument
46 initSubtargetFeatures(CPU, FS); in initializeSubtargetDependencies()
50 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU, in PPCSubtarget() argument
52 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), in PPCSubtarget()
55 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)), in PPCSubtarget()
115 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { in initSubtargetFeatures() argument
117 std::string CPUName = CPU; in initSubtargetFeatures()
118 if (CPUName.empty() || CPU == "generic") { in initSubtargetFeatures()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp114 StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) { in selectHexagonCPU() argument
116 if (!ArchV.empty() && !CPU.empty()) { in selectHexagonCPU()
117 if (ArchV != CPU) in selectHexagonCPU()
119 return CPU; in selectHexagonCPU()
122 if (CPU.empty()) in selectHexagonCPU()
123 CPU = DefaultArch; in selectHexagonCPU()
124 return CPU; in selectHexagonCPU()
279 std::string selectHexagonFS(StringRef CPU, StringRef FS) { in selectHexagonFS() argument
301 Result.push_back(StringSwitch<StringRef>(CPU) in selectHexagonFS()
316 static bool isCPUValid(std::string CPU) in isCPUValid() argument
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