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Searched refs:CONCAT_VECTORS (Results 1 – 22 of 22) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp97 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
131 setOperationAction(ISD::CONCAT_VECTORS, T, Custom); in initializeHVXLowering()
188 setOperationAction(ISD::CONCAT_VECTORS, BoolV, Custom); in initializeHVXLowering()
253 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
901 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1}); in insertHvxSubvectorReg()
902 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV}); in insertHvxSubvectorReg()
1036 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1); in LowerHvxBuildVector()
1104 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1106 SDValue V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, in LowerHvxConcatVectors()
1469 SDValue S = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, L, H); in SplitHvxPairOp()
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H A DHexagonISelLowering.cpp1433 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE in HexagonTargetLowering()
1478 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); in HexagonTargetLowering()
2761 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAGHVX.cpp1430 LV = DAG.getNode(ISD::CONCAT_VECTORS, dl, ResTy, {L0, L1}); in scalarizeShuffle()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp546 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
1001 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); in SplitVecRes_CONCAT_VECTORS()
1004 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); in SplitVecRes_CONCAT_VECTORS()
1875 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
2355 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
2656 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, in CollectOpsToWiden()
3164 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops); in WidenVecRes_CONCAT_VECTORS()
3371 else if (N.getOpcode() == ISD::CONCAT_VECTORS) { in isSETCCorConvertedSETCC()
4296 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, in GenWidenVectorLoads()
4310 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps); in GenWidenVectorLoads()
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H A DDAGCombiner.cpp1584 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); in visit()
7555 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
7556 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
7596 ISD::CONCAT_VECTORS, DL, VT, in ConvertSelectToConcatVector()
8042 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
8043 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
9840 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { in visitTRUNCATE()
17079 if (V.getOpcode() == ISD::CONCAT_VECTORS && in visitEXTRACT_SUBVECTOR()
17224 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops); in partitionShuffleOfConcats()
17682 if (N0.getOpcode() == ISD::CONCAT_VECTORS && in visitVECTOR_SHUFFLE()
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H A DSelectionDAGDumper.cpp274 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
H A DSelectionDAG.cpp2400 case ISD::CONCAT_VECTORS: { in computeKnownBits()
3696 case ISD::CONCAT_VECTORS: { in ComputeNumSignBits()
4268 case ISD::CONCAT_VECTORS: in getNode()
4793 case ISD::CONCAT_VECTORS: { in getNode()
4981 N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
5082 if (N2C && N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
5278 case ISD::CONCAT_VECTORS: { in getNode()
7100 case ISD::CONCAT_VECTORS: in getNode()
H A DLegalizeIntegerTypes.cpp104 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
833 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
1052 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
H A DLegalizeDAG.cpp2900 case ISD::CONCAT_VECTORS: in ExpandNode()
4408 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps); in PromoteNode()
4530 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts); in PromoteNode()
H A DSelectionDAGBuilder.cpp408 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
3269 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, ConcatOps)); in visitShuffleVector()
3289 : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps1); in visitShuffleVector()
3292 : DAG.getNode(ISD::CONCAT_VECTORS, DL, PaddedVT, MOps2); in visitShuffleVector()
H A DTargetLowering.cpp546 case ISD::CONCAT_VECTORS: { in SimplifyDemandedBits()
1597 case ISD::CONCAT_VECTORS: { in SimplifyDemandedVectorElts()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h345 CONCAT_VECTORS, enumerator
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp8662 ISD::CONCAT_VECTORS, DL, VT, in createVariablePermute()
9294 assert(Op.getOpcode() == ISD::CONCAT_VECTORS && in isExpandWithZeros()
9310 assert(Opc == ISD::CONCAT_VECTORS && in isTypePromotionOfi1ZeroUpBits()
11691 case ISD::CONCAT_VECTORS: { in lowerVectorShuffleAsBroadcast()
17987 In = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), in LowerAVXExtend()
19268 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in Lower256IntVSETCC()
23246 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in LowerVectorIntUnary()
23501 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in split256IntArith()
23530 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, in split512IntArith()
25874 if (InOp.getOpcode() == ISD::CONCAT_VECTORS && in ExtendToType()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp330 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); in AMDGPUTargetLowering()
331 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); in AMDGPUTargetLowering()
332 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); in AMDGPUTargetLowering()
333 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in AMDGPUTargetLowering()
1146 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
1414 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad), in SplitVectorLoad()
H A DSIISelLowering.cpp265 case ISD::CONCAT_VECTORS: in SITargetLowering()
511 case ISD::CONCAT_VECTORS: in SITargetLowering()
3594 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitUnaryVectorOp()
3617 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi); in splitBinaryVectorOp()
5112 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads); in lowerSBuffer()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp570 setTargetDAGCombine(ISD::CONCAT_VECTORS); in AArch64TargetLowering()
789 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
2797 SDValue TruncExt = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16, in LowerTruncateVectorStore()
6019 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6401 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1); in tryFormConcatFromShuffle()
6539 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst); in GenerateTBL()
6547 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); in GenerateTBL()
6623 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) { in LowerVECTOR_SHUFFLE()
9527 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy, in performConcatVectorsCombine()
10091 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
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H A DAArch64InstrFormats.td8586 // intrinsic, represented by CONCAT_VECTORS.
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp177 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
6540 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper); in LowerBUILD_VECTOR()
6676 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
7031 if (V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) { in LowerVECTOR_SHUFFLE()
7536 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
7572 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
8047 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
9854 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT, in AddCombineVUZPToVPADDL()
11522 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
11523 Op1.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp600 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td544 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp899 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand); in PPCTargetLowering()
948 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand); in PPCTargetLowering()
989 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand); in PPCTargetLowering()
7303 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops); in widenVec()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2089 case ISD::CONCAT_VECTORS: in LowerOperation()