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Searched refs:BuildMI (Results 1 – 25 of 247) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp190 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
213 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
275 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doMaskedAtomicBinOpExpansion()
322 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
325 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
393 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)) in expandAtomicMinMaxOp()
401 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE)) in expandAtomicMinMaxOp()
434 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)) in expandAtomicMinMaxOp()
490 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE)) in expandAtomicCmpXchg()
500 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE)) in expandAtomicCmpXchg()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DShadowCallStack.cpp95 BuildMI(MBB, MBBI, DL, TII->get(X86::XOR64rr)) in addProlog()
117 addDirectMem(BuildMI(MBB, MBB.begin(), DL, TII->get(X86::MOV64rm)) in addPrologLeaf()
127 BuildMI(MBB, MI, DL, TII->get(X86::XOR64rr)) in addEpilog()
139 addSegmentedMem(BuildMI(MBB, MI, DL, TII->get(X86::SUB64mi8)), in addEpilog()
143 addDirectMem(BuildMI(MBB, MI, DL, TII->get(X86::CMP64mr)), X86::RSP) in addEpilog()
146 BuildMI(MBB, MI, DL, TII->get(X86::JNE_1)).addMBB(&TrapBB); in addEpilog()
156 addDirectMem(BuildMI(MBB, MI, DL, TII->get(X86::CMP64mr)), X86::RSP) in addEpilogLeaf()
159 BuildMI(MBB, MI, DL, TII->get(X86::JNE_1)).addMBB(&TrapBB); in addEpilogLeaf()
168 BuildMI(MBB, MI, DL, TII->get(X86::XOR64rr)) in addEpilogOnlyR10()
186 BuildMI(MBB, MI, DL, TII->get(X86::JNE_1)).addMBB(&TrapBB); in addEpilogOnlyR10()
[all …]
H A DX86FrameLowering.cpp293 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r)) in emitSPUpdate()
332 BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
378 MI = addRegOffset(BuildMI(MBB, MBBI, DL, in BuildStackAdjustment()
701 BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi)) in emitStackProbeInline()
710 BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr)) in emitStackProbeInline()
793 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)) in emitStackProbeCall()
1134 BuildMI(MBB, MBBI, DL, in emitPrologue()
1494 BuildMI(MBB, MBBI, DL, TII.get(X86::CLD)) in emitPrologue()
2173 BuildMI(MBB, MI, DL, TII.get(Opc), Reg) in restoreCalleeSavedRegisters()
2643 BuildMI(incStackMBB, DL, TII.get(CALLop)). in adjustForHiPEPrologue()
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H A DX86ExpandPseudo.cpp86 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11) in ExpandICallBranchFunnel()
93 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr)) in ExpandICallBranchFunnel()
120 BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64)) in ExpandICallBranchFunnel()
162 BuildMI(P.first, DL, TII->get(X86::TAILJMPd64)) in ExpandICallBranchFunnel()
257 BuildMI(MBB, MBBI, DL, in ExpandMI()
261 BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr)) in ExpandMI()
280 BuildMI(MBB, MBBI, DL, in ExpandMI()
291 BuildMI(MBB, MBBI, DL, in ExpandMI()
301 MIB = BuildMI(MBB, MBBI, DL, in ExpandMI()
304 MIB = BuildMI(MBB, MBBI, DL, in ExpandMI()
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/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp904 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
909 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
914 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
921 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
944 BuildMI(MBB, MBBI, dl, OrInst, BPReg) in emitPrologue()
1099 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
1104 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
1109 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
1179 BuildMI(MBB, MBBI, dl, OrInst, FPReg) in emitPrologue()
1405 BuildMI(MBB, MBBI, dl, AddInst) in emitEpilogue()
[all …]
H A DPPCRegisterInfo.cpp461 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg) in lowerDynamicAlloc()
465 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
469 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) in lowerDynamicAlloc()
473 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
490 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) in lowerDynamicAlloc()
501 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
515 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) in lowerDynamicAlloc()
526 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) in lowerDynamicAlloc()
770 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) in lowerVRSAVESpilling()
801 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) in lowerVRSAVERestore()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsBranchExpansion.cpp341 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
388 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
460 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
486 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); in expandToLongBranch()
524 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP)); in expandToLongBranch()
583 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)) in expandToLongBranch()
597 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); in expandToLongBranch()
657 BuildMI(*LongBrMBB, Pos, DL, in expandToLongBranch()
669 .append(BuildMI(*MFp, DL, TII->get(Mips::NOP))); in expandToLongBranch()
725 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp()
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H A DMipsExpandPseudo.cpp150 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwapSubword()
164 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwapSubword()
168 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwapSubword()
176 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicCmpSwapSubword()
184 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest) in expandAtomicCmpSwapSubword()
280 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwap()
288 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwap()
290 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwap()
443 BuildMI(loopMBB, DL, TII->get(SC), StoreVal) in expandAtomicBinOpSubword()
445 BuildMI(loopMBB, DL, TII->get(BEQ)) in expandAtomicBinOpSubword()
[all …]
H A DMipsSEFrameLowering.cpp217 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); in expandLoadACC()
219 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
239 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandStoreACC()
241 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
273 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandCopyACC()
274 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
277 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
440 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
553 BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP) in emitPrologue()
759 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB)); in emitInterruptEpilogueStub()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp64 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
80 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
84 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0) in emitPrologue()
87 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
90 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
139 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitPrologue()
171 BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr)) in emitEpilogue()
215 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitEpilogue()
265 BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr)) in spillCalleeSavedRegisters()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp37 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
79 BuildMI(*BB, MI, dl, get(LdOpc)) in expandMEMCPY()
82 BuildMI(*BB, MI, dl, get(StOpc)) in expandMEMCPY()
93 BuildMI(*BB, MI, dl, get(BPF::LDW)) in expandMEMCPY()
95 BuildMI(*BB, MI, dl, get(BPF::STW)) in expandMEMCPY()
100 BuildMI(*BB, MI, dl, get(BPF::LDH)) in expandMEMCPY()
102 BuildMI(*BB, MI, dl, get(BPF::STH)) in expandMEMCPY()
107 BuildMI(*BB, MI, dl, get(BPF::LDB)) in expandMEMCPY()
109 BuildMI(*BB, MI, dl, get(BPF::STB)) in expandMEMCPY()
135 BuildMI(MBB, I, DL, get(BPF::STD)) in storeRegToStackSlot()
[all …]
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h320 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
336 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
359 return BuildMI(BB, *I, DL, MCID, DestReg); in BuildMI()
365 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
375 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
392 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID); in BuildMI()
398 return BuildMI(BB, *I, DL, MCID); in BuildMI()
405 return BuildMI(*BB, BB->end(), DL, MCID); in BuildMI()
413 return BuildMI(*BB, BB->end(), DL, MCID, DestReg); in BuildMI()
435 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
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/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp256 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); in insertBranch()
264 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); in insertBranch()
266 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); in insertBranch()
270 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); in insertBranch()
323 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
331 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
335 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
346 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
362 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg) in copyPhysReg()
367 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg) in copyPhysReg()
[all …]
H A DSparcFrameLowering.cpp52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
163 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
186 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased) in emitPrologue()
193 BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased) in emitPrologue()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp262 BuildMI(MBB, std::next(Info.I), dl, in emitDefCFAOffsets()
533 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL)) in emitPrologue()
1201 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Spills()
1270 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64)) in emitAlignedDPRCS2Spills()
1283 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD)) in emitAlignedDPRCS2Spills()
1354 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4) in emitAlignedDPRCS2Restores()
2338 BuildMI(GetMBB, DL, TII.get(Opcode)) in adjustForSegmentedStacks()
2383 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH)) in adjustForSegmentedStacks()
2407 BuildMI(AllocMBB, DL, TII.get(ARM::tBL)) in adjustForSegmentedStacks()
2411 BuildMI(AllocMBB, DL, TII.get(ARM::BL)) in adjustForSegmentedStacks()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp71 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr) in generateStackAdjustment()
137 BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6)) in emitPrologue()
144 BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9)) in emitPrologue()
155 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); in emitPrologue()
156 BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6)) in emitPrologue()
160 BuildMI(MBB, MBBI, dl, TII->get(ARC::BL)) in emitPrologue()
169 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); in emitPrologue()
182 BuildMI(MBB, MBBI, dl, in emitPrologue()
196 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
282 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(ARC::BL)) in emitEpilogue()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp418 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)) in expandMOVImm()
622 BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg()) in expandCMP_SWAP()
624 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
628 BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc)) in expandCMP_SWAP()
638 BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg) in expandCMP_SWAP()
641 BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW)) in expandCMP_SWAP()
701 BuildMI(LoadCmpBB, DL, TII->get(AArch64::LDAXPX)) in expandCMP_SWAP_128()
721 BuildMI(LoadCmpBB, DL, TII->get(AArch64::CBNZW)) in expandCMP_SWAP_128()
730 BuildMI(StoreBB, DL, TII->get(AArch64::STLXPX), StatusReg) in expandCMP_SWAP_128()
734 BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW)) in expandCMP_SWAP_128()
[all …]
H A DAArch64FrameLowering.cpp549 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveReg)) in InsertSEH()
983 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BL)) in emitPrologue()
1004 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BLR)) in emitPrologue()
1207 BuildMI(MBB, MBBI, DL, in InsertReturnAddressAuth()
1212 BuildMI( in InsertReturnAddressAuth()
1368 BuildMI(MBB, MBB.getFirstTerminator(), DL, in emitEpilogue()
1402 BuildMI(MBB, MBB.getFirstTerminator(), DL, in emitEpilogue()
1745 BuildMI(MBB, MI, DL, TII.get(AArch64::STRXpost)) in spillCalleeSavedRegisters()
1753 BuildMI(MBB, MI, DL, TII.get(AArch64::SEH_Nop)) in spillCalleeSavedRegisters()
1945 BuildMI(MBB, MI, DL, TII.get(AArch64::LDRXpre)) in restoreCalleeSavedRegisters()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp67 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) in emitPrologue()
99 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
136 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); in emitEpilogue()
157 BuildMI(MBB, MBBI, DL, in emitEpilogue()
161 BuildMI(MBB, MBBI, DL, in emitEpilogue()
171 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) in emitEpilogue()
200 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) in spillCalleeSavedRegisters()
221 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg()); in restoreCalleeSavedRegisters()
257 New = BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::ADD16ri), in eliminateCallFramePseudoInstr()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp387 BuildMI(MBB, I, DL, SMovB32, RsrcHi) in emitEntryFunctionScratchSetup()
392 BuildMI(MBB, I, DL, GetPC64, Rsrc01); in emitEntryFunctionScratchSetup()
409 BuildMI(MBB, I, DL, SMovB32, RsrcLo) in emitEntryFunctionScratchSetup()
426 BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg) in emitEntryFunctionScratchSetup()
451 BuildMI(MBB, I, DL, Mov64, Rsrc01) in emitEntryFunctionScratchSetup()
466 BuildMI(MBB, I, DL, LoadDwordX2, Rsrc01) in emitEntryFunctionScratchSetup()
477 BuildMI(MBB, I, DL, SMovB32, Rsrc0) in emitEntryFunctionScratchSetup()
481 BuildMI(MBB, I, DL, SMovB32, Rsrc1) in emitEntryFunctionScratchSetup()
487 BuildMI(MBB, I, DL, SMovB32, Rsrc2) in emitEntryFunctionScratchSetup()
491 BuildMI(MBB, I, DL, SMovB32, Rsrc3) in emitEntryFunctionScratchSetup()
[all …]
H A DSIInstrInfo.cpp927 BuildMI(MBB, MI, DL, get(Opcode)) in storeRegToStackSlot()
1020 BuildMI(MBB, MI, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
1133 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP)) in insertWaitStates()
1152 BuildMI(MBB, MBB.end(), DebugLoc(), in insertReturn()
1251 BuildMI(MBB, MI, DL, MovRelDesc) in expandPostRAPseudo()
1748 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)) in insertBranch()
1770 BuildMI(&MBB, DL, get(Opcode)) in insertBranch()
1784 BuildMI(&MBB, DL, get(Opcode)) in insertBranch()
1786 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)) in insertBranch()
1920 MachineInstrBuilder MIB = BuildMI( in insertSelect()
[all …]
H A DSILowerControlFlow.cpp194 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg) in emitIf()
201 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_AND_B64), Tmp) in emitIf()
210 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_XOR_B64), SaveExecReg) in emitIf()
219 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64_term), AMDGPU::EXEC) in emitIf()
271 BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg) in emitElse()
288 BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::S_AND_B64), DstReg) in emitElse()
302 BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::SI_MASK_BRANCH)) in emitElse()
351 And = BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_B64), Dst) in emitIfBreak()
354 Or = BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) in emitIfBreak()
358 Or = BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) in emitIfBreak()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp836 BuildMI(B, MI, DL, TII->get(A2_aslh), LoR) in splitShift()
839 BuildMI(B, MI, DL, TII->get(A2_asrh), TmpR) in splitShift()
859 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR) in splitShift()
863 BuildMI(B, MI, DL, TII->get(S2_insert), LoR) in splitShift()
876 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR) in splitShift()
882 BuildMI(B, MI, DL, TII->get(A2_aslh), HiR) in splitShift()
885 BuildMI(B, MI, DL, TII->get(A2_asrh), LoR) in splitShift()
946 BuildMI(B, MI, DL, TII->get(A2_or), LoR) in splitAslOr()
949 BuildMI(B, MI, DL, TII->get(A2_or), HiR) in splitAslOr()
963 BuildMI(B, MI, DL, TII->get(A2_or), TmpR2) in splitAslOr()
[all …]
H A DHexagonCopyToCombine.cpp660 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::CONST64), DoubleDestReg) in emitConst64()
673 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
680 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) in emitCombineII()
689 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
696 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) in emitCombineII()
705 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
711 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) in emitCombineII()
753 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
801 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg) in emitCombineIR()
850 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg) in emitCombineRI()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp71 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
77 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
84 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
184 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertSPConstInst()
[all …]

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