Lines Matching refs:BuildMI
502 BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg) in reportIllegalCopy()
515 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) in copyPhysReg()
523 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg) in copyPhysReg()
534 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) in copyPhysReg()
542 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) in copyPhysReg()
547 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32)) in copyPhysReg()
560 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) in copyPhysReg()
567 BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32)) in copyPhysReg()
600 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, in copyPhysReg()
641 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) in materializeImmediate()
649 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) in materializeImmediate()
655 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) in materializeImmediate()
660 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg) in materializeImmediate()
681 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, in materializeImmediate()
704 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
706 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in insertVectorSelect()
715 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
718 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in insertVectorSelect()
726 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
729 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in insertVectorSelect()
739 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
741 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in insertVectorSelect()
751 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg) in insertVectorSelect()
753 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in insertVectorSelect()
762 BuildMI(MBB, I, DL, get(AMDGPU::S_OR_SAVEEXEC_B64), SReg2) in insertVectorSelect()
764 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
767 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in insertVectorSelect()
776 BuildMI(MBB, I, DL, get(AMDGPU::S_OR_SAVEEXEC_B64), SReg2) in insertVectorSelect()
778 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), SReg) in insertVectorSelect()
781 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in insertVectorSelect()
802 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg) in insertEQ()
815 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg) in insertNE()
904 MachineInstrBuilder Spill = BuildMI(MBB, MI, DL, OpDesc) in storeRegToStackSlot()
927 BuildMI(MBB, MI, DL, get(Opcode)) in storeRegToStackSlot()
1003 MachineInstrBuilder Spill = BuildMI(MBB, MI, DL, OpDesc, DestReg) in loadRegFromStackSlot()
1020 BuildMI(MBB, MI, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
1069 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0) in calculateLDSSpillAddress()
1072 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1) in calculateLDSSpillAddress()
1077 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1) in calculateLDSSpillAddress()
1081 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg) in calculateLDSSpillAddress()
1085 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg) in calculateLDSSpillAddress()
1095 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64), in calculateLDSSpillAddress()
1100 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64), in calculateLDSSpillAddress()
1106 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32), in calculateLDSSpillAddress()
1133 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP)) in insertWaitStates()
1152 BuildMI(MBB, MBB.end(), DebugLoc(), in insertReturn()
1199 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
1202 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
1207 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
1210 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
1218 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC) in expandPostRAPseudo()
1220 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1222 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC) in expandPostRAPseudo()
1228 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC) in expandPostRAPseudo()
1230 MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), in expandPostRAPseudo()
1234 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOT_B64), AMDGPU::EXEC) in expandPostRAPseudo()
1251 BuildMI(MBB, MI, DL, MovRelDesc) in expandPostRAPseudo()
1275 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg)); in expandPostRAPseudo()
1279 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo) in expandPostRAPseudo()
1283 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi) in expandPostRAPseudo()
1488 MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg); in insertIndirectBranch()
1492 BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32)) in insertIndirectBranch()
1496 BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32)) in insertIndirectBranch()
1502 BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32)) in insertIndirectBranch()
1506 BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32)) in insertIndirectBranch()
1513 BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64)) in insertIndirectBranch()
1748 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)) in insertBranch()
1756 BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO)) in insertBranch()
1770 BuildMI(&MBB, DL, get(Opcode)) in insertBranch()
1784 BuildMI(&MBB, DL, get(Opcode)) in insertBranch()
1786 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH)) in insertBranch()
1873 BuildMI(MBB, I, DL, get(SelOp), DstReg) in insertSelect()
1883 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg) in insertSelect()
1920 MachineInstrBuilder MIB = BuildMI( in insertSelect()
1933 BuildMI(MBB, I, DL, get(SelOp), DstElt) in insertSelect()
2322 return BuildMI(*MBB, MI, MI.getDebugLoc(), in convertToThreeAddress()
2330 return BuildMI(*MBB, MI, MI.getDebugLoc(), in convertToThreeAddress()
2340 return BuildMI(*MBB, MI, MI.getDebugLoc(), in convertToThreeAddress()
2352 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc)) in convertToThreeAddress()
2667 BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32)); in buildShrunkInst()
3310 BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO); in legalizeOpWithMove()
3326 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) in buildExtractSubReg()
3337 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg) in buildExtractSubReg()
3340 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) in buildExtractSubReg()
3493 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg) in legalizeOperandsVOP2()
3500 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg) in legalizeOperandsVOP2()
3519 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg) in legalizeOperandsVOP2()
3622 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), in readlaneVGPRToSGPR()
3631 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), in readlaneVGPRToSGPR()
3638 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), in readlaneVGPRToSGPR()
3684 BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).add(Op); in legalizeGenericOperand()
3721 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0) in emitLoadSRsrcFromVGPRLoop()
3723 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub1) in emitLoadSRsrcFromVGPRLoop()
3725 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub2) in emitLoadSRsrcFromVGPRLoop()
3727 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub3) in emitLoadSRsrcFromVGPRLoop()
3730 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc) in emitLoadSRsrcFromVGPRLoop()
3745 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg0) in emitLoadSRsrcFromVGPRLoop()
3748 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg1) in emitLoadSRsrcFromVGPRLoop()
3751 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_AND_B64), AndCond) in emitLoadSRsrcFromVGPRLoop()
3758 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_AND_SAVEEXEC_B64), SaveExec) in emitLoadSRsrcFromVGPRLoop()
3765 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_XOR_B64_term), AMDGPU::EXEC) in emitLoadSRsrcFromVGPRLoop()
3768 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(&LoopBB); in emitLoadSRsrcFromVGPRLoop()
3784 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_MOV_B64), SaveExec) in loadSRsrcFromVGPR()
3834 BuildMI(*RemainderBB, First, DL, TII.get(AMDGPU::S_MOV_B64), AMDGPU::EXEC) in loadSRsrcFromVGPR()
3858 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64) in extractRsrcPtr()
3862 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatLo) in extractRsrcPtr()
3866 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatHi) in extractRsrcPtr()
3870 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::REG_SEQUENCE), NewSRsrc) in extractRsrcPtr()
4066 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), NewVAddrLo) in legalizeOperands()
4071 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e32), NewVAddrHi) in legalizeOperands()
4076 BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr) in legalizeOperands()
4108 BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode)) in legalizeOperands()
4132 Addr64 = BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode)) in legalizeOperands()
4146 BuildMI(MBB, Addr64, Addr64->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), in legalizeOperands()
4293 BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B64), in moveToVALU()
4485 BuildMI(MBB, MII, DL, get(SubOp), TmpReg) in lowerScalarAbs()
4489 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg) in lowerScalarAbs()
4513 BuildMI(MBB, MII, DL, get(AMDGPU::V_XNOR_B32_e64), NewDest) in lowerScalarXnor()
4537 Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp) in lowerScalarXnor()
4539 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest) in lowerScalarXnor()
4543 Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp) in lowerScalarXnor()
4545 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest) in lowerScalarXnor()
4549 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), Temp) in lowerScalarXnor()
4552 Not = BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest) in lowerScalarXnor()
4580 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), Interm) in splitScalarNotBinop()
4584 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest) in splitScalarNotBinop()
4609 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Interm) in splitScalarBinOpN2()
4612 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), NewDest) in splitScalarBinOpN2()
4650 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp()
4656 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp()
4659 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitUnaryOp()
4716 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0) in splitScalar64BitAddSub()
4723 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1) in splitScalar64BitAddSub()
4729 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitAddSub()
4785 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp()
4790 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp()
4795 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitBinaryOp()
4838 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B64), Interm) in splitScalar64BitXnor()
4843 MachineInstr &Xor = *BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B64), NewDest) in splitScalar64BitXnor()
4878 BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0); in splitScalar64BitBCNT()
4880 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg); in splitScalar64BitBCNT()
4912 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo) in splitScalar64BitBFE()
4917 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi) in splitScalar64BitBFE()
4921 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
4936 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg) in splitScalar64BitBFE()
4940 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
4985 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
4988 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_B32_e64), TmpReg) in movePackToVALU()
4992 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32), ResultReg) in movePackToVALU()
5000 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
5002 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_BFI_B32), ResultReg) in movePackToVALU()
5011 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg) in movePackToVALU()
5014 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg) in movePackToVALU()
5016 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32), ResultReg) in movePackToVALU()
5348 BuildMI(*MF, Branch->getDebugLoc(), get(AMDGPU::SI_IF), DstReg) in convertNonUniformIfRegion()
5352 BuildMI(*MF, Branch->getDebugLoc(), get(AMDGPU::SI_END_CF)) in convertNonUniformIfRegion()
5376 BuildMI(*(MF), Branch->getDebugLoc(), get(TargetOpcode::PHI), DstReg); in convertNonUniformLoopRegion()
5392 MachineInstr *SIIFBREAK = BuildMI(*(MF), Branch->getDebugLoc(), in convertNonUniformLoopRegion()
5397 BuildMI(*(MF), Branch->getDebugLoc(), get(AMDGPU::SI_LOOP)) in convertNonUniformLoopRegion()
5463 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e64), DestReg); in getAddNoCarry()
5469 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_I32_e64), DestReg) in getAddNoCarry()