| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrFMA3Info.cpp | 136 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group() local
141 ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) || in getFMA3Group()
142 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) || in getFMA3Group()
143 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF)); in getFMA3Group()
160 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3; in getFMA3Group()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | MIMGInstructions.td | 27 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
52 let PrimaryKey = ["BaseOpcode"];
112 MIMGBaseOpcode BaseOpcode;
141 let d16 = !if(BaseOpcode.HasD16, ?, 0);
148 #!if(BaseOpcode.HasD16, "$d16", "");
173 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
195 let d16 = !if(BaseOpcode.HasD16, ?, 0);
232 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
303 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
318 let d16 = !if(BaseOpcode.HasD16, ?, 0);
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| H A D | AMDGPUInstrInfo.h | 54 unsigned BaseOpcode; member
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| H A D | AMDGPUInstructionSelector.cpp | 448 static unsigned getSmrdOpcode(unsigned BaseOpcode, unsigned LoadSize) { in getSmrdOpcode() argument
451 return BaseOpcode; in getSmrdOpcode()
453 switch (BaseOpcode) { in getSmrdOpcode()
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| H A D | SIISelLowering.cpp | 4795 if (BaseOpcode->Atomic) { in lowerImage()
4799 if (BaseOpcode->AtomicX2) { in lowerImage()
4823 if (BaseOpcode->Store) { in lowerImage()
4829 !BaseOpcode->HasD16) in lowerImage()
4843 !BaseOpcode->HasD16) in lowerImage()
4928 if (!BaseOpcode->Sampler) { in lowerImage()
4990 if (BaseOpcode->Atomic) { in lowerImage()
5000 if (BaseOpcode->Store || BaseOpcode->Atomic) in lowerImage()
5004 if (BaseOpcode->Sampler) in lowerImage()
5015 if (BaseOpcode->HasD16) in lowerImage()
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| H A D | BUFInstructions.td | 309 Instruction BaseOpcode = !cast<Instruction>(MUBUFGetBaseOpcode<NAME>.ret);
2097 let Fields = ["Opcode", "BaseOpcode", "dwords", "has_vaddr", "has_srsrc", "has_soffset"];
2110 let Key = ["BaseOpcode", "dwords"];
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFPU.td | 261 let BaseOpcode = "RECIP_D32";
273 let BaseOpcode = "RSQRT_D32";
284 let BaseOpcode = "LDC132";
298 let BaseOpcode = "c.f."#NAME;
303 let BaseOpcode = "c.un."#NAME;
308 let BaseOpcode = "c.eq."#NAME;
313 let BaseOpcode = "c.ueq."#NAME;
318 let BaseOpcode = "c.olt."#NAME;
334 let BaseOpcode = "c.sf."#NAME;
352 let BaseOpcode = "c.lt."#NAME;
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| H A D | MipsEVAInstrInfo.td | 62 string BaseOpcode = instr_asm;
81 string BaseOpcode = instr_asm;
98 string BaseOpcode = instr_asm;
116 string BaseOpcode = instr_asm;
132 string BaseOpcode = instr_asm;
146 string BaseOpcode = instr_asm;
172 string BaseOpcode = instr_asm;
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| H A D | MipsInstrFPU.td | 284 let BaseOpcode = "c.f."#NAME;
289 let BaseOpcode = "c.un."#NAME;
294 let BaseOpcode = "c.eq."#NAME;
299 let BaseOpcode = "c.ueq."#NAME;
320 let BaseOpcode = "c.sf."#NAME;
338 let BaseOpcode = "c.lt."#NAME;
346 let BaseOpcode = "c.le."#NAME;
389 let BaseOpcode = "RECIP_D32";
399 let BaseOpcode = "RSQRT_D32";
574 let BaseOpcode = "LDC164";
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| H A D | MipsDSPInstrInfo.td | 268 string BaseOpcode = instr_asm;
279 string BaseOpcode = instr_asm;
290 string BaseOpcode = instr_asm;
301 string BaseOpcode = instr_asm;
313 string BaseOpcode = instr_asm;
324 string BaseOpcode = instr_asm;
335 string BaseOpcode = instr_asm;
345 string BaseOpcode = instr_asm;
357 string BaseOpcode = instr_asm;
368 string BaseOpcode = instr_asm;
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| H A D | MicroMips32r6InstrInfo.td | 613 string BaseOpcode = opstr;
663 string BaseOpcode = opstr;
676 string BaseOpcode = opstr;
687 string BaseOpcode = opstr;
699 string BaseOpcode = opstr;
721 string BaseOpcode = opstr;
734 string BaseOpcode = opstr;
743 string BaseOpcode = opstr;
788 string BaseOpcode = opstr;
802 string BaseOpcode = opstr;
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| H A D | MipsDSPInstrFormats.td | 14 // Instructions with the same BaseOpcode and isNVStore values form a row.
15 let RowFields = ["BaseOpcode"];
50 string BaseOpcode = opstr;
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| H A D | MipsInstrFormats.td | 43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
57 // Instructions with the same BaseOpcode and isNVStore values form a row.
58 let RowFields = ["BaseOpcode"];
124 string BaseOpcode = opstr;
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| H A D | Mips32r6InstrFormats.td | 18 // Instructions with the same BaseOpcode and isNVStore values form a row.
19 let RowFields = ["BaseOpcode"];
30 string BaseOpcode = opstr;
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| H A D | MicroMipsInstrInfo.td | 218 let BaseOpcode = opstr;
229 let BaseOpcode = opstr;
271 string BaseOpcode = opstr;
287 string BaseOpcode = opstr;
592 let BaseOpcode = opstr;
597 let BaseOpcode = opstr;
604 let BaseOpcode = opstr;
611 let BaseOpcode = opstr;
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| H A D | MicroMipsDSPInstrFormats.td | 14 string BaseOpcode = opstr;
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| H A D | MipsInstrInfo.td | 1436 string BaseOpcode = opstr;
1450 string BaseOpcode = opstr;
1468 let BaseOpcode = opstr;
1476 let BaseOpcode = opstr;
1905 let BaseOpcode = asmstr;
1912 let BaseOpcode = asmstr;
2612 let BaseOpcode = opstr;
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| H A D | MicroMips32r6InstrFormats.td | 16 string BaseOpcode = opstr;
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | Hexagon.td | 129 // Instructions with the same BaseOpcode and isNVStore values form a row.
130 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
145 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
157 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
169 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
181 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
193 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
205 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
287 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
295 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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| H A D | HexagonDepInstrInfo.td | 56 let BaseOpcode = "A2_add";
220 let BaseOpcode = "A2_addi";
306 let BaseOpcode = "A2_and";
345 let BaseOpcode = "A2_aslh";
591 let BaseOpcode = "A2_or";
635 let BaseOpcode = "A2_add";
652 let BaseOpcode = "A2_add";
833 let BaseOpcode = "A2_or";
848 let BaseOpcode = "A2_or";
861 let BaseOpcode = "A2_or";
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| H A D | HexagonPseudo.td | 169 let BaseOpcode = "call";
201 BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2 in
299 isBarrier = 1, BaseOpcode = "JMPret" in {
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| H A D | HexagonInstrFormats.td | 171 string BaseOpcode = "";
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 1295 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1308 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1318 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1322 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1336 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1343 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1351 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1364 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1379 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1394 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 182 MIMGBaseOpcode BaseOpcode; member
197 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
218 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
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| H A D | AMDGPUBaseInfo.cpp | 104 uint16_t BaseOpcode; member
116 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, in getMIMGOpcode() argument
118 const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding, in getMIMGOpcode()
126 getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding, in getMaskedMIMGOp()
133 uint16_t BaseOpcode; member
146 return Info ? Info->BaseOpcode : -1; in getMUBUFBaseOpcode()
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