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Searched refs:BaseOpc (Results 1 – 6 of 6) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td965 def NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
966 def NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
967 def NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
1100 def NAME#8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>;
1102 def NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>;
1103 def NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>;
1104 def NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
1132 def NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>;
1133 def NAME#16mr : BinOpMR_F<BaseOpc, mnemonic, Xi16, opnode>;
1134 def NAME#32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>;
[all …]
H A DX86FastISel.cpp2903 unsigned BaseOpc, CondOpc; in fastLowerIntrinsicCall() local
2907 BaseOpc = ISD::ADD; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2909 BaseOpc = ISD::ADD; CondOpc = X86::SETBr; break; in fastLowerIntrinsicCall()
2911 BaseOpc = ISD::SUB; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2913 BaseOpc = ISD::SUB; CondOpc = X86::SETBr; break; in fastLowerIntrinsicCall()
2915 BaseOpc = X86ISD::SMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2917 BaseOpc = X86ISD::UMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2933 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) && in fastLowerIntrinsicCall()
2937 bool IsDec = BaseOpc == ISD::SUB; in fastLowerIntrinsicCall()
2959 if (BaseOpc == X86ISD::UMUL && !ResultReg) { in fastLowerIntrinsicCall()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp697 int BaseOpc = in CreateLoadStoreMulti() local
705 BaseOpc = in CreateLoadStoreMulti()
727 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
745 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
747 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
752 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
758 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h228 int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords);
H A DAMDGPUBaseInfo.cpp149 int getMUBUFOpcode(unsigned BaseOpc, unsigned Dwords) { in getMUBUFOpcode() argument
150 const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndDwords(BaseOpc, Dwords); in getMUBUFOpcode()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp2658 unsigned BaseOpc = BO.first.getOpcode(); in LowerUnalignedLoad() local
2659 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0) in LowerUnalignedLoad()
2667 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR) in LowerUnalignedLoad()