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Searched refs:BaseOffs (Results 1 – 19 of 19) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp1967 if (BaseOffs != other.BaseOffs) in compare()
2040 BaseOffs = 0; in SetCombinedField()
2066 if (BaseOffs) { in print()
2068 << BaseOffs; in print()
4004 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
4035 AddrMode.BaseOffs -= ConstantOffset; in matchOperationAddr()
4044 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
4069 AddrMode.BaseOffs += ConstantOffset; in matchOperationAddr()
4152 AddrMode.BaseOffs += CI->getSExtValue(); in matchAddr()
4723 if (AddrMode.BaseOffs) { in optimizeMemoryInst()
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H A DTargetLoweringBase.cpp1601 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
1613 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1618 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1887 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1892 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1899 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1902 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1907 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1910 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1914 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1917 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUPerfHintAnalysis.cpp247 auto *Ptr = GetPointerBaseWithConstantOffset(GEP, AM.BaseOffs, *DL); in visit()
H A DSILoadStoreOptimizer.cpp1370 AM.BaseOffs = Dist; in promoteConstantOffsetToImm()
1395 AM.BaseOffs = P.second - AnchorAddr.Offset; in promoteConstantOffsetToImm()
H A DSIISelLowering.cpp961 return AM.BaseOffs == 0 && AM.Scale == 0; in isLegalFlatAddressingMode()
968 return isUInt<12>(AM.BaseOffs) && AM.Scale == 0; in isLegalFlatAddressingMode()
973 return isInt<13>(AM.BaseOffs) && AM.Scale == 0; in isLegalGlobalAddressingMode()
1001 if (!isUInt<12>(AM.BaseOffs)) in isLegalMUBUFAddressingMode()
1041 if (AM.BaseOffs % 4 != 0) in isLegalAddressingMode()
1053 if (!isUInt<8>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1058 if (!isUInt<32>(AM.BaseOffs / 4)) in isLegalAddressingMode()
1062 if (!isUInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
1083 if (!isUInt<16>(AM.BaseOffs)) in isLegalAddressingMode()
7109 AM.BaseOffs = Offset.getSExtValue(); in performSHLPtrCombine()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h231 AM.BaseOffs = BaseOffset;
257 AM.BaseOffs = BaseOffset; in getScalingFactorCost()
H A DTargetLowering.h2070 int64_t BaseOffs = 0; member
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp493 if (AM.BaseOffs < 0) in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp2945 if ((AM.BaseOffs % A) != 0) in isLegalAddressingMode()
2948 if (!isInt<11>(AM.BaseOffs >> Log2_32(A))) in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp216 if (!isInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp748 int64_t Offs = AM.BaseOffs; in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp13735 if (Ty->isVectorTy() && AM.BaseOffs != 0) in isLegalAddressingMode()
13739 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
13751 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
13756 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp712 if (!isInt<20>(AM.BaseOffs)) in isLegalAddressingMode()
719 if (!SupportedAM.LongDisplacement && !isUInt<12>(AM.BaseOffs)) in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp3964 return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale; in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp8656 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) in isLegalAddressingMode()
8670 int64_t Offset = AM.BaseOffs; in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13273 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
13285 if (AM.BaseOffs) in isLegalAddressingMode()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp12562 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode()
12570 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp27421 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr)) in isLegalAddressingMode()
27438 Subtarget.is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()