| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 57 AssertSext, AssertZext, enumerator
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatterns.td | 685 def AssertZextSD: SDNode<"ISD::AssertZext", SDTAssertZext>;
686 class AssertZext<ValueType T>: PatFrag<(ops node:$A), (AssertZextSD $A, T)>;
713 defm: Cmpb_pat <A4_cmpbeqi, seteq, AssertZext<i8>, IsUGT<8,31>, 255>;
714 defm: CmpbN_pat <A4_cmpbeqi, setne, AssertZext<i8>, IsUGT<8,31>, 255>;
715 defm: Cmpb_pat <A4_cmpbgtui, setugt, AssertZext<i8>, IsUGT<32,31>, 255>;
716 defm: CmpbN_pat <A4_cmpbgtui, setule, AssertZext<i8>, IsUGT<32,31>, 255>;
717 defm: Cmpb_pat <A4_cmphgtui, setugt, AssertZext<i16>, IsUGT<32,31>, 65535>;
718 defm: CmpbN_pat <A4_cmphgtui, setule, AssertZext<i16>, IsUGT<32,31>, 65535>;
719 defm: CmpbND_pat<A4_cmpbgtui, setult, AssertZext<i8>, IsUGT<32,32>, 255>;
720 defm: CmpbND_pat<A4_cmphgtui, setult, AssertZext<i16>, IsUGT<32,32>, 65535>;
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| H A D | HexagonISelDAGToDAG.cpp | 1508 case ISD::AssertZext: in keepsLowBits()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 108 case ISD::AssertZext: return "AssertZext"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 58 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
198 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
490 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
1517 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
2230 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
2234 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
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| H A D | LegalizeVectorOps.cpp | 577 Promoted = DAG.getNode(Op->getOpcode() == ISD::FP_TO_UINT ? ISD::AssertZext in PromoteFP_TO_INT()
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| H A D | SelectionDAGBuilder.cpp | 862 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
4936 case ISD::AssertZext: in getUnderlyingArgReg()
8041 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), Op, in lowerRangeToAssertZExt()
8739 AssertOp = ISD::AssertZext; in LowerCallTo()
9225 AssertOp = ISD::AssertZext; in LowerArguments()
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| H A D | LegalizeDAG.cpp | 750 Result = DAG.getNode(ISD::AssertZext, dl, in LegalizeLoadOps()
2764 LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res, in ExpandNode()
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| H A D | SelectionDAGISel.cpp | 2968 case ISD::AssertZext: in SelectCodeCommon()
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| H A D | TargetLowering.cpp | 1232 case ISD::AssertZext: { in SimplifyDemandedBits()
2593 if (Op0.getOpcode() == ISD::AssertZext && in SimplifySetCC()
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| H A D | DAGCombiner.cpp | 1107 case ISD::AssertZext: in PromoteOperand()
1109 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1)); in PromoteOperand()
1545 case ISD::AssertZext: return visitAssertExt(N); in visit()
4357 case ISD::AssertZext: { in SearchForAndLoads()
4360 EVT VT = Op.getOpcode() == ISD::AssertZext ? in SearchForAndLoads()
9273 Opcode == ISD::AssertZext) { in visitAssertExt()
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| H A D | SelectionDAG.cpp | 2856 case ISD::AssertZext: { in computeKnownBits()
3309 case ISD::AssertZext: in ComputeNumSignBits()
4911 case ISD::AssertZext: { in getNode()
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| /freebsd-12.1/contrib/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 250 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 557 (RHS->getOpcode() == ISD::AssertZext && in PerformDAGCombine()
563 DAG.getNode(ISD::AssertZext, DL, RHS.getValueType(), RHS, in PerformDAGCombine()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 1314 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext; in convertArgType()
1986 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg, in LowerFormalArguments()
2016 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val, in LowerFormalArguments()
2035 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val, in LowerFormalArguments()
2240 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
4586 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param, in lowerImplicitZextParam()
7302 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE, in performAndCombine()
9182 if (Op.getOpcode() == ISD::AssertZext) in isFrameIndexOp()
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| H A D | AMDGPUISelLowering.cpp | 535 setTargetDAGCombine(ISD::AssertZext); in AMDGPUTargetLowering()
3985 case ISD::AssertZext: in PerformDAGCombine()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 507 setTargetDAGCombine(ISD::AssertZext); in MipsTargetLowering()
3306 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
3368 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
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| /freebsd-12.1/contrib/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 647 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1104 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 617 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1333 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrCompiler.td | 1340 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
1347 N->getOpcode() != ISD::AssertZext;
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| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 571 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 1362 case ISD::AssertZext: { in getValueBits()
2734 (Input.getOperand(0).getOpcode() == ISD::AssertZext || in zeroExtendInputIfNeeded()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 3737 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
12790 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
12793 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
12796 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
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