| /freebsd-12.1/contrib/llvm/include/llvm/Support/ |
| H A D | Allocator.h | 252 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); in Allocate() local
253 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); in Allocate()
254 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
262 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); in Allocate() local
263 assert(AlignedAddr + SizeToAllocate <= (uintptr_t)End && in Allocate()
265 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 128 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
134 Value *AlignedAddr, Value *CmpVal,
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| H A D | RISCVISelLowering.cpp | 1755 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
1758 Type *Tys[] = {AlignedAddr->getType()}; in emitMaskedAtomicRMWIntrinsic()
1776 {AlignedAddr, Incr, Mask, SextShamt, Ordering}); in emitMaskedAtomicRMWIntrinsic()
1779 return Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering}); in emitMaskedAtomicRMWIntrinsic()
1792 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, in emitMaskedAtomicCmpXchgIntrinsic() argument
1795 Type *Tys[] = {AlignedAddr->getType()}; in emitMaskedAtomicCmpXchgIntrinsic()
1799 {AlignedAddr, CmpVal, NewVal, Mask, Ordering}); in emitMaskedAtomicCmpXchgIntrinsic()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | AtomicExpandPass.cpp | 589 Value *AlignedAddr; member
636 Ret.AlignedAddr = Builder.CreateIntToPtr( in createMaskInstrs()
741 insertRMWCmpXchgLoop(Builder, PMV.WordType, PMV.AlignedAddr, MemOpOrder, in expandPartwordAtomicRMW()
774 AtomicRMWInst *NewAI = Builder.CreateAtomicRMW(Op, PMV.AlignedAddr, in widenPartwordAtomicRMW()
853 LoadInst *InitLoaded = Builder.CreateLoad(PMV.WordType, PMV.AlignedAddr); in expandPartwordCmpXchg()
867 PMV.AlignedAddr, FullWord_Cmp, FullWord_NewVal, CI->getSuccessOrdering(), in expandPartwordCmpXchg()
940 Builder, AI, PMV.AlignedAddr, ValOperand_Shifted, PMV.Mask, PMV.ShiftAmt, in expandAtomicRMWToMaskedIntrinsic()
962 Builder, CI, PMV.AlignedAddr, CmpVal_Shifted, NewVal_Shifted, PMV.Mask, in expandAtomicCmpXchgToMaskedIntrinsic()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1575 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicBinaryPartword() local
1661 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) in emitAtomicBinaryPartword()
1687 .addReg(AlignedAddr) in emitAtomicBinaryPartword()
1787 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicCmpSwapPartword() local
1844 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) in emitAtomicCmpSwapPartword()
1876 .addReg(AlignedAddr) in emitAtomicCmpSwapPartword()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1619 Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
1629 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, in emitMaskedAtomicCmpXchgIntrinsic() argument
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3460 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_LOAD_OP() local
3489 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
3576 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_CMP_SWAP() local
3592 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift, in lowerATOMIC_CMP_SWAP()
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