Searched refs:AFGR64RegClass (Results 1 – 9 of 9) sorted by relevance
52 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); in MipsRegInfoRecord()71 const MCRegisterClass *AFGR64RegClass; variable
186 for (RegIter Reg = Mips::AFGR64RegClass.begin(), in getReservedRegs()187 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg) in getReservedRegs()
320 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()385 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()463 if (Mips::AFGR64RegClass.contains(Reg)) { in emitPrologue()
146 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()274 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()352 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
401 const TargetRegisterClass *RC = &Mips::AFGR64RegClass; in materializeFP()786 ResultReg = createResultReg(&Mips::AFGR64RegClass); in emitLoad()1013 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass); in selectFPExt()1042 RC = &Mips::AFGR64RegClass; in selectSelect()1443 Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++); in fastLowerArguments()
335 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8; in printSavedRegsBitmask()348 } else if (Mips::AFGR64RegClass.contains(Reg)) { in printSavedRegsBitmask()
3852 if (RC == &Mips::AFGR64RegClass) { in parseRegForInlineAsmConstraint()3906 return std::make_pair(0U, &Mips::AFGR64RegClass); in getRegForInlineAsmConstraint()
179 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); in MipsSETargetLowering()
93 AFGR64RegClass->contains(CurrentSubReg) || in SetPhysRegUsed()