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/f-stack/freebsd/contrib/device-tree/Bindings/timer/
H A Drockchip,rk-timer.txt1 Rockchip rk timer
5 "rockchip,rv1108-timer", "rockchip,rk3288-timer": for Rockchip RV1108
6 "rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036
7 "rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066
8 "rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188
9 "rockchip,rk3228-timer", "rockchip,rk3288-timer": for Rockchip RK3228
10 "rockchip,rk3229-timer", "rockchip,rk3288-timer": for Rockchip RK3229
12 "rockchip,rk3368-timer", "rockchip,rk3288-timer": for Rockchip RK3368
18 "timer", "pclk"
21 timer: timer@ff810000 {
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H A Dti,timer.txt5 OMAP44xx devices have timer instances that are 100%
8 So for OMAP44xx devices timer instances may use
23 - ti,hwmods: Name of the hwmod associated to the timer, "timer<X>",
28 - ti,timer-alwon: Indicates the timer is in an alway-on power domain.
29 - ti,timer-dsp: Indicates the timer can interrupt the on-chip DSP in
31 - ti,timer-pwm: Indicates the timer can generate a PWM output.
32 - ti,timer-secure: Indicates the timer is reserved on a secure OMAP device
37 timer12: timer@48304000 {
38 compatible = "ti,omap3430-timer";
42 ti,timer-alwon;
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H A Dmediatek,mtk-timer.txt8 The proper timer will be selected automatically by driver.
13 * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
14 * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
15 * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
16 * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT)
17 * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
18 * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
19 * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
20 * "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
33 timer@10008000 {
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H A Dsnps,dw-apb-timer.yaml4 $id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml#
15 - const: snps,dw-apb-timer
17 - snps,dw-apb-timer-sp
18 - snps,dw-apb-timer-osc
36 - const: timer
66 timer@ffe00000 {
67 compatible = "snps,dw-apb-timer";
71 clock-names = "timer", "pclk";
74 timer@ffe00000 {
79 clock-names = "timer";
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H A Dcirrus,clps711x-timer.txt4 - compatible: Shall contain "cirrus,ep7209-timer".
6 - interrupts: The interrupt number of the timer.
7 - clocks : phandle of timer reference clock.
9 Note: Each timer should have an alias correctly numbered in "aliases" node.
17 timer1: timer@80000300 {
18 compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
24 timer2: timer@80000340 {
25 compatible = "cirrus,ep7312-timer", "cirrus,ep7209-timer";
H A Dlsi,zevio-timer.txt1 TI-NSPIRE timer
5 - compatible : should be "lsi,zevio-timer".
6 - reg : The physical base address and size of the timer (always first).
11 - interrupts : The interrupt number of the first timer.
13 (always after timer base address)
15 If any of the optional properties are not given, the timer is added as a
20 timer {
21 compatible = "lsi,zevio-timer";
29 timer {
30 compatible = "lsi,zevio-timer";
H A Dallwinner,sun4i-a10-timer.yaml4 $id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml#
16 - allwinner,sun4i-a10-timer
17 - allwinner,sun8i-a23-timer
18 - allwinner,sun8i-v3s-timer
19 - allwinner,suniv-f1c100s-timer
36 const: allwinner,sun4i-a10-timer
48 const: allwinner,sun8i-a23-timer
60 const: allwinner,sun8i-v3s-timer
72 const: allwinner,suniv-f1c100s-timer
90 timer@1c20c00 {
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H A Dqcom,msm-timer.txt5 - compatible : Should at least contain "qcom,msm-timer". More specific
8 "qcom,kpss-timer" - krait subsystem
9 "qcom,scss-timer" - scorpion subsystem
11 - interrupts : Interrupts for the debug timer, the first general purpose
12 timer, and optionally a second general purpose timer, and
15 - reg : Specifies the base address of the timer registers.
23 - clock-frequency : The frequency of the debug timer and the general purpose
24 timer(s) in Hz in that order.
28 - cpu-offset : per-cpu offset used when the timer is accessed without the
34 timer@200a000 {
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H A Dnuvoton,npcm7xx-timer.txt1 Nuvoton NPCM7xx timer
3 Nuvoton NPCM7xx have three timer modules, each timer module provides five 24-bit
4 timer counters.
7 - compatible : "nuvoton,npcm750-timer" for Poleg NPCM750.
9 - interrupts : Contain the timer interrupt with flags for
11 - clocks : phandle of timer reference clock (usually a 25 MHz clock).
15 timer@f0008000 {
16 compatible = "nuvoton,npcm750-timer";
H A Dfaraday,fttmr010.txt1 Faraday Technology timer
3 This timer is a generic IP block from Faraday Technology, embedded in the
10 "cortina,gemini-timer", "faraday,fttmr010"
11 "moxa,moxart-timer", "faraday,fttmr010"
12 "aspeed,ast2400-timer"
13 "aspeed,ast2500-timer"
14 "aspeed,ast2600-timer"
17 - interrupts : Should contain the three timer interrupts usually with
23 - clock-names : should be "EXTCLK" and "PCLK" for the external tick timer
26 type is "cortina,gemini-timer"
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H A Drenesas,16bit-timer.txt1 * Renesas H8/300 16bit timer
3 The 16bit timer is a 16bit timer/counter with configurable clock inputs and
8 - compatible: must contain "renesas,16bit-timer"
9 - reg: base address and length of the registers block for the timer module.
10 - interrupts: interrupt-specifier for the timer, IMIA
13 - renesas,channel: timer channel number.
17 timer16: timer@ffff68 {
18 compatible = "reneas,16bit-timer";
H A Darm,mps2-timer.txt1 ARM MPS2 timer
6 - compatible : Should be "arm,mps2-timer"
8 - interrupts : Reference to the timer interrupt
11 - clocks : The input clock of the timer
12 - clock-frequency : The rate in HZ in input of the ARM MPS2 timer
16 timer1: mps2-timer@40000000 {
17 compatible = "arm,mps2-timer";
23 timer2: mps2-timer@40001000 {
24 compatible = "arm,mps2-timer";
H A Dnvidia,tegra30-timer.txt1 NVIDIA Tegra30 timer
3 The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
9 - compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise,
10 must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where
13 - interrupts : A list of 6 interrupts; one per each of timer channels 1
18 timer {
19 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
H A Dmarvell,armada-370-xp-timer.txt6 "marvell,armada-370-timer",
7 "marvell,armada-375-timer",
8 "marvell,armada-xp-timer".
10 then local timer interrupts
15 Clocks required for compatible = "marvell,armada-370-timer":
18 Clocks required for compatibles = "marvell,armada-xp-timer",
19 "marvell,armada-375-timer":
29 timer {
30 compatible = "marvell,armada-370-timer";
38 timer {
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H A Darm,arch_timer.yaml7 title: ARM architected timer
26 - arm,cortex-a15-timer
28 - arm,armv7-timer
31 - arm,armv7-timer
34 - arm,armv8-timer
38 - description: secure timer irq
39 - description: non-secure timer irq
40 - description: virtual timer irq
41 - description: hypervisor timer irq
101 timer {
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H A Dti,keystone-timer.txt1 * Device tree bindings for Texas instruments Keystone timer
3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 It is global timer is a free running up-counter and can generate interrupt
17 - compatible : should be "ti,keystone-timer".
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
24 timer@22f0000 {
25 compatible = "ti,keystone-timer";
/f-stack/app/nginx-1.16.1/src/event/
H A Dngx_event_timer.h36 ngx_event_ident(ev->data), ev->timer.key); in ngx_event_del_timer()
38 ngx_rbtree_delete(&ngx_event_timer_rbtree, &ev->timer); in ngx_event_del_timer()
41 ev->timer.left = NULL; in ngx_event_del_timer()
42 ev->timer.right = NULL; in ngx_event_del_timer()
43 ev->timer.parent = NULL; in ngx_event_del_timer()
51 ngx_event_add_timer(ngx_event_t *ev, ngx_msec_t timer) in ngx_event_add_timer() argument
56 key = ngx_current_msec + timer; in ngx_event_add_timer()
66 diff = (ngx_msec_int_t) (key - ev->timer.key); in ngx_event_add_timer()
78 ev->timer.key = key; in ngx_event_add_timer()
82 ngx_event_ident(ev->data), timer, ev->timer.key); in ngx_event_add_timer()
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H A Dngx_event_timer.c35 ngx_msec_int_t timer; in ngx_event_find_timer() local
47 timer = (ngx_msec_int_t) (node->key - ngx_current_msec); in ngx_event_find_timer()
49 return (ngx_msec_t) (timer > 0 ? timer : 0); in ngx_event_find_timer()
76 ev = (ngx_event_t *) ((char *) node - offsetof(ngx_event_t, timer)); in ngx_event_expire_timers()
80 ngx_event_ident(ev->data), ev->timer.key); in ngx_event_expire_timers()
82 ngx_rbtree_delete(&ngx_event_timer_rbtree, &ev->timer); in ngx_event_expire_timers()
85 ev->timer.left = NULL; in ngx_event_expire_timers()
86 ev->timer.right = NULL; in ngx_event_expire_timers()
87 ev->timer.parent = NULL; in ngx_event_expire_timers()
116 ev = (ngx_event_t *) ((char *) node - offsetof(ngx_event_t, timer)); in ngx_event_no_timers_left()
/f-stack/freebsd/amd64/vmm/io/
H A Dvhpet.c96 } timer[VHPET_NUM_TIMERS]; member
262 compval = vhpet->timer[n].compval; in vhpet_adjust_compval()
263 comprate = vhpet->timer[n].comprate; in vhpet_adjust_compval()
278 vhpet->timer[n].compval = compnext; in vhpet_adjust_compval()
294 callout = &vhpet->timer[n].callout; in vhpet_handler()
345 if (vhpet->timer[n].comprate != 0) in vhpet_start_timer()
359 callout_reset_sbt(&vhpet->timer[n].callout, vhpet->timer[n].callout_sbt, in vhpet_start_timer()
440 vhpet->timer[n].comprate = 0; in vhpet_timer_update_config()
682 data = vhpet->timer[i].compval; in vhpet_mmio_read()
688 data = vhpet->timer[i].msireg; in vhpet_mmio_read()
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/f-stack/dpdk/doc/guides/prog_guide/
H A Devent_timer_adapter.rst34 device upon timer expiration.
54 the timer expiry event
129 used by the timer adapter. If required, the
144 or maximum timer expiry timeout based on the given event timer adapter or
205 /* Set up the event timer. */
221 timer itself.
251 * cancel the retransmission timer
258 Once an event timer has successfully enqueued a timer expiry event in the event
261 associated with the event timer. It can then re-arm the event timer or free the
262 event timer object as desired:
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/f-stack/app/redis-5.0.5/deps/jemalloc/test/src/
H A Dtimer.c4 timer_start(timedelta_t *timer) { in timer_start() argument
5 nstime_init(&timer->t0, 0); in timer_start()
6 nstime_update(&timer->t0); in timer_start()
10 timer_stop(timedelta_t *timer) { in timer_stop() argument
11 nstime_copy(&timer->t1, &timer->t0); in timer_stop()
12 nstime_update(&timer->t1); in timer_stop()
16 timer_usec(const timedelta_t *timer) { in timer_usec() argument
19 nstime_copy(&delta, &timer->t1); in timer_usec()
20 nstime_subtract(&delta, &timer->t0); in timer_usec()
/f-stack/freebsd/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmpic-timer.txt4 - compatible: "fsl,mpic-global-timer"
6 - reg : Contains two regions. The first is the main timer register bank
7 (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
11 timer interrupts can be used. This property is optional; without this,
14 - interrupts: one interrupt per timer in the group, in order, starting
15 with timer zero. If timer-available-ranges is present, only the
20 timer0: timer@41100 {
21 compatible = "fsl,mpic-global-timer";
31 timer1: timer@42100 {
32 compatible = "fsl,mpic-global-timer";
/f-stack/freebsd/contrib/device-tree/src/arm/
H A Domap2.dtsi225 timer2: timer@0 {
232 timer3: timer@48078000 {
239 timer4: timer@4807a000 {
251 ti,timer-dsp;
259 ti,timer-dsp;
267 ti,timer-dsp;
275 ti,timer-dsp;
283 ti,timer-pwm;
291 ti,timer-pwm;
299 ti,timer-pwm;
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/f-stack/freebsd/contrib/device-tree/Bindings/soc/microchip/
H A Datmel,at91rm9200-tcb.yaml54 "^timer@[0-2]$":
61 - atmel,tcb-timer
122 tcb0: timer@fff7c000 {
131 timer@0 {
136 timer@2 {
143 tcb1: timer@fffdc000 {
152 timer@0 {
157 timer@1 {
163 timer@f800c000 {
172 timer@0 {
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/f-stack/dpdk/app/test/
H A Dtest_timer_racecond.c56 static struct rte_timer timer[N_TIMERS]; variable
64 RTE_LOG_REGISTER(timer_logtype_test, test.timer, INFO);
71 if (tim == &timer[0]) in timer_cb()
75 PRIuPTR "\n", __func__, rte_lcore_id(), tim - timer); in timer_cb()
90 (tim - timer); in reload_timer()
97 rte_lcore_id(), tim - timer); in reload_timer()
117 if (rte_timer_pending(&timer[0])) { in worker_main_loop()
127 (void)reload_timer(&timer[i]); in worker_main_loop()
155 rte_timer_init(&timer[i]); in test_timer_racecond()
156 ret = reload_timer(&timer[i]); in test_timer_racecond()
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