Home
last modified time | relevance | path

Searched refs:encp (Results 1 – 25 of 42) sorted by relevance

12

/f-stack/dpdk/drivers/common/sfc_efx/base/
H A Dhunt_nic.c73 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in hunt_board_cfg() local
108 encp->enc_bug35388_workaround = B_TRUE; in hunt_board_cfg()
121 encp->enc_bug41750_workaround = B_TRUE; in hunt_board_cfg()
133 if (EFX_PCI_FUNCTION_IS_VF(encp)) { in hunt_board_cfg()
135 encp->enc_bug41750_workaround = B_TRUE; in hunt_board_cfg()
147 if (encp->enc_bug35388_workaround) { in hunt_board_cfg()
148 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in hunt_board_cfg()
151 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in hunt_board_cfg()
158 encp->enc_bug61297_workaround = B_TRUE; in hunt_board_cfg()
165 encp->enc_rx_buf_align_start = 1; in hunt_board_cfg()
[all …]
H A Dmedford_nic.c39 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in medford_board_cfg() local
68 if (EFX_PCI_FUNCTION_IS_VF(encp)) { in medford_board_cfg()
73 encp->enc_bug41750_workaround = B_TRUE; in medford_board_cfg()
84 encp->enc_bug61265_workaround = B_TRUE; in medford_board_cfg()
86 encp->enc_bug61265_workaround = B_FALSE; in medford_board_cfg()
91 encp->enc_bug61297_workaround = B_TRUE; in medford_board_cfg()
102 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in medford_board_cfg()
110 encp->enc_rx_buf_align_start = 1; in medford_board_cfg()
120 encp->enc_rx_buf_align_end = end_padding; in medford_board_cfg()
122 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS; in medford_board_cfg()
[all …]
H A Dmedford2_nic.c41 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in medford2_board_cfg() local
70 if (EFX_PCI_FUNCTION_IS_VF(encp)) { in medford2_board_cfg()
75 encp->enc_bug41750_workaround = B_TRUE; in medford2_board_cfg()
86 encp->enc_bug61265_workaround = B_TRUE; in medford2_board_cfg()
88 encp->enc_bug61265_workaround = B_FALSE; in medford2_board_cfg()
93 encp->enc_bug61297_workaround = B_FALSE; in medford2_board_cfg()
104 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in medford2_board_cfg()
112 encp->enc_rx_buf_align_start = 1; in medford2_board_cfg()
122 encp->enc_rx_buf_align_end = end_padding; in medford2_board_cfg()
124 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS; in medford2_board_cfg()
[all …]
H A Drhead_nic.c50 encp->enc_tx_dma_desc_boundary = 0; in rhead_board_cfg()
58 encp->enc_tx_tso_max_header_ndescs = in rhead_board_cfg()
66 encp->enc_tx_tso_max_nframes = in rhead_board_cfg()
80 encp->enc_evq_limit = 1024; in rhead_board_cfg()
130 encp->enc_evq_timer_max_us = 0; in rhead_board_cfg()
135 encp->enc_ev_ew_desc_size = 0; in rhead_board_cfg()
143 encp->enc_rx_push_align = 1; in rhead_board_cfg()
149 encp->enc_rx_buf_align_start = 1; in rhead_board_cfg()
162 encp->enc_rx_scatter_max = 7; in rhead_board_cfg()
168 encp->enc_vpd_is_global = B_TRUE; in rhead_board_cfg()
[all …]
H A Dsiena_nic.c82 encp->enc_board_type = board_type; in siena_board_cfg()
89 encp->enc_hw_pf_count = 1; in siena_board_cfg()
92 encp->enc_clk_mult = 1; in siena_board_cfg()
98 encp->enc_clk_mult = 2; in siena_board_cfg()
102 encp->enc_evq_timer_quantum_ns = in siena_board_cfg()
104 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << in siena_board_cfg()
112 encp->enc_rx_prefix_size = 16; in siena_board_cfg()
116 encp->enc_rx_buf_align_end = 1; in siena_board_cfg()
119 encp->enc_rx_push_align = 1; in siena_board_cfg()
158 encp->enc_evq_limit = nevq; in siena_board_cfg()
[all …]
H A Def10_nic.c1083 encp->enc_rx_prefix_size = 14; in ef10_get_datapath_caps()
1085 encp->enc_rx_prefix_size = 0; in ef10_get_datapath_caps()
1151 encp->enc_rx_batch_max = 16; in ef10_get_datapath_caps()
1160 encp->enc_rx_scatter_max = -1; in ef10_get_datapath_caps()
1482 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf, in ef10_get_privilege_mask()
1850 encp->enc_assigned_port = port; in efx_mcdi_nic_board_cfg()
1865 encp->enc_pf = pf; in efx_mcdi_nic_board_cfg()
1866 encp->enc_vf = vf; in efx_mcdi_nic_board_cfg()
1950 encp->enc_intr_limit = nvec; in efx_mcdi_nic_board_cfg()
2139 encp->enc_evq_limit = 1024; in ef10_nic_board_cfg()
[all …]
H A Dmcdi_mon.c434 encp->enc_mcdi_sensor_maskp, in mcdi_mon_stats_update()
435 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_stats_update()
580 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_build()
581 encp->enc_mcdi_sensor_maskp); in mcdi_mon_cfg_build()
590 encp->enc_mcdi_sensor_maskp, in mcdi_mon_cfg_build()
596 encp->enc_mcdi_sensor_maskp, in mcdi_mon_cfg_build()
597 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_build()
605 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_build()
606 encp->enc_mcdi_sensor_maskp); in mcdi_mon_cfg_build()
628 encp->enc_mcdi_sensor_mask_size, in mcdi_mon_cfg_free()
[all …]
H A Defx_nic.c406 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_nic_probe() local
440 encp->enc_features = enp->en_features; in efx_nic_probe()
562 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in efx_nic_get_vi_pool() local
580 *evq_countp = encp->enc_evq_limit; in efx_nic_get_vi_pool()
581 *rxq_countp = encp->enc_rxq_limit; in efx_nic_get_vi_pool()
582 *txq_countp = encp->enc_txq_limit; in efx_nic_get_vi_pool()
1018 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mcdi_get_loopback_modes() local
1057 encp->enc_loopback_types[EFX_LINK_100FDX] = modes; in efx_mcdi_get_loopback_modes()
1061 encp->enc_loopback_types[EFX_LINK_1000FDX] = modes; in efx_mcdi_get_loopback_modes()
1116 encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes; in efx_mcdi_get_loopback_modes()
[all …]
H A Defx_ev.c210 desc_size = encp->enc_ev_desc_size; in efx_evq_size()
214 desc_size = encp->enc_ev_ew_desc_size; in efx_evq_size()
277 if (index >= encp->enc_evq_limit) { in efx_ev_qcreate()
282 if (us > encp->enc_evq_timer_max_us) { in efx_ev_qcreate()
302 (encp->enc_ev_ew_desc_size == 0)) { in efx_ev_qcreate()
312 ndescs < encp->enc_evq_min_nevs || in efx_ev_qcreate()
313 ndescs > encp->enc_evq_max_nevs) { in efx_ev_qcreate()
476 const efx_nic_cfg_t *encp; in efx_ev_qcreate_check_init_done() local
483 encp = efx_nic_cfg_get(eep->ee_enp); in efx_ev_qcreate_check_init_done()
1235 if (us > encp->enc_evq_timer_max_us) { in siena_ev_qmoderate()
[all …]
H A Def10_mac.c224 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_mac_pdu_set() local
227 if (encp->enc_enhanced_set_mac_supported) { in ef10_mac_pdu_set()
470 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_mac_stats_get_mask() local
487 if (encp->enc_mac_stats_40g_tx_size_bins) { in ef10_mac_stats_get_mask()
499 if (encp->enc_pm_and_rxdp_counters) { in ef10_mac_stats_get_mask()
509 if (encp->enc_datapath_cap_evb) { in ef10_mac_stats_get_mask()
520 if (encp->enc_fec_counters) { in ef10_mac_stats_get_mask()
541 if (encp->enc_hlb_counters) { in ef10_mac_stats_get_mask()
585 const efx_nic_cfg_t *encp = &enp->en_nic_cfg; in ef10_mac_stats_update() local
608 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) { in ef10_mac_stats_update()
[all …]
H A Defx_rx.c340 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in efx_rx_scale_hash_flags_get() local
570 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in efx_rx_scale_mode_set() local
810 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in efx_rxq_size() local
812 return (ndescs * encp->enc_rx_desc_size); in efx_rxq_size()
859 EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs)); in efx_rx_qcreate_internal()
860 EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs)); in efx_rx_qcreate_internal()
862 if (index >= encp->enc_rxq_limit) { in efx_rx_qcreate_internal()
868 ndescs < encp->enc_rxq_min_ndescs || in efx_rx_qcreate_internal()
869 ndescs > encp->enc_rxq_max_ndescs) { in efx_rx_qcreate_internal()
1710 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_rx_qcreate() local
[all …]
H A Defx_tx.c338 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in efx_txq_size() local
340 return (ndescs * encp->enc_tx_desc_size); in efx_txq_size()
375 EFSYS_ASSERT(ISP2(encp->enc_txq_max_ndescs)); in efx_tx_qcreate()
376 EFSYS_ASSERT(ISP2(encp->enc_txq_min_ndescs)); in efx_tx_qcreate()
379 ndescs < encp->enc_txq_min_ndescs || in efx_tx_qcreate()
380 ndescs > encp->enc_txq_max_ndescs) { in efx_tx_qcreate()
883 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_tx_qpace() local
896 timer_period = 104 / encp->enc_clk_mult; in siena_tx_qpace()
977 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_tx_qcreate() local
989 if (index >= encp->enc_txq_limit) { in siena_tx_qcreate()
[all …]
H A Dsiena_sram.c16 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_sram_init() local
23 rx_base = encp->enc_buftbl_limit; in siena_sram_init()
24 tx_base = rx_base + (encp->enc_rxq_limit * in siena_sram_init()
H A Defx_mon.c27 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mon_name() local
31 EFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID); in efx_mon_name()
32 EFSYS_ASSERT3U(encp->enc_mon_type, <, EFX_MON_NTYPES); in efx_mon_name()
33 return (__efx_mon_name[encp->enc_mon_type]); in efx_mon_name()
52 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_mon_init() local
67 emp->em_type = encp->enc_mon_type; in efx_mon_init()
69 EFSYS_ASSERT(encp->enc_mon_type != EFX_MON_INVALID); in efx_mon_init()
H A Defx_mcdi.c1642 (void) memset(encp->enc_phy_name, 0, in efx_mcdi_get_phy_cfg()
1643 sizeof (encp->enc_phy_name)); in efx_mcdi_get_phy_cfg()
1646 (void) memset(encp->enc_phy_revision, 0, in efx_mcdi_get_phy_cfg()
1647 sizeof (encp->enc_phy_revision)); in efx_mcdi_get_phy_cfg()
1648 memcpy(encp->enc_phy_revision, in efx_mcdi_get_phy_cfg()
1680 encp->enc_mcdi_mdio_channel = in efx_mcdi_get_phy_cfg()
1684 encp->enc_mcdi_phy_stat_mask = in efx_mcdi_get_phy_cfg()
1689 encp->enc_bist_mask = 0; in efx_mcdi_get_phy_cfg()
2600 if (encp->enc_init_evq_v2_supported) { in efx_mcdi_init_evq()
2718 if (encp->enc_init_evq_v2_supported) { in efx_mcdi_init_evq()
[all …]
H A Def10_mcdi.c110 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_mcdi_get_timeout() local
117 if (encp->enc_nvram_update_verify_result_supported != B_FALSE) { in ef10_mcdi_get_timeout()
291 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_mcdi_feature_supported() local
292 uint32_t privilege_mask = encp->enc_privilege_mask; in ef10_mcdi_feature_supported()
H A Defx_mae.c245 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in efx_mae_init() local
253 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_init()
325 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); in efx_mae_fini() local
328 if (encp->enc_mae_supported == B_FALSE) in efx_mae_fini()
348 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_get_limits()
1420 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_outer_rule_insert()
1519 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_outer_rule_remove()
1606 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_action_set_alloc()
1723 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_action_set_free()
1785 if (encp->enc_mae_supported == B_FALSE) { in efx_mae_action_rule_insert()
[all …]
H A Def10_rx.c149 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in efx_mcdi_rss_context_set_flags() local
190 if (encp->enc_rx_scale_additional_modes_supported == B_FALSE) in efx_mcdi_rss_context_set_flags()
444 efx_nic_cfg_t *encp = &enp->en_nic_cfg; in ef10_rx_scale_mode_set() local
449 if ((encp->enc_rx_scale_hash_alg_mask & (1U << alg)) == 0 || in ef10_rx_scale_mode_set()
908 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_rx_qcreate() local
998 if (encp->enc_rx_packed_stream_supported == B_FALSE) { in ef10_rx_qcreate()
1004 (encp->enc_rx_var_packed_stream_supported == B_FALSE)) { in ef10_rx_qcreate()
1015 if (encp->enc_rx_es_super_buffer_supported == B_FALSE) { in ef10_rx_qcreate()
1038 params.disable_scatter = encp->enc_rx_disable_scatter_supported; in ef10_rx_qcreate()
H A Def10_intr.c96 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in ef10_intr_trigger() local
99 if (encp->enc_bug41750_workaround) { in ef10_intr_trigger()
H A Defx_phy.c76 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in efx_phy_probe() local
82 epp->ep_port = encp->enc_port; in efx_phy_probe()
83 epp->ep_phy_type = encp->enc_phy_type; in efx_phy_probe()
155 efx_nic_cfg_t *encp = (&enp->en_nic_cfg); in efx_phy_led_set() local
168 mask |= encp->enc_led_mask; in efx_phy_led_set()
H A Defx_tunnel.c322 const efx_nic_cfg_t *encp = &enp->en_nic_cfg; in efx_tunnel_config_udp_add() local
335 if ((encp->enc_tunnel_encapsulations_supported & in efx_tunnel_config_udp_add()
350 encp->enc_tunnel_config_udp_entries_max) { in efx_tunnel_config_udp_add()
645 const efx_nic_cfg_t *encp = &enp->en_nic_cfg; in ef10_udp_encap_supported() local
651 return ((encp->enc_tunnel_encapsulations_supported & in ef10_udp_encap_supported()
H A Dsiena_phy.c525 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); in siena_phy_stats_update() local
526 uint32_t vmask = encp->enc_mcdi_phy_stat_mask; in siena_phy_stats_update()
558 EFSYS_ASSERT(smask == encp->enc_phy_stat_mask); in siena_phy_stats_update()
623 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); variable
656 encp->enc_phy_type == EFX_PHY_SFT9001B &&
735 encp->enc_phy_type == EFX_PHY_QLX111V &&
/f-stack/dpdk/drivers/net/sfc/
H A Dsfc.c205 MIN(encp->enc_txq_limit, in sfc_estimate_resource_limits()
211 encp->enc_fw_assisted_tso_v2_n_contexts / in sfc_estimate_resource_limits()
212 encp->enc_hw_pf_count); in sfc_estimate_resource_limits()
328 const efx_nic_cfg_t *encp; in sfc_try_start() local
351 encp = efx_nic_cfg_get(sa->nic); in sfc_try_start()
359 encp->enc_tunnel_encapsulations_supported; in sfc_try_start()
762 const efx_nic_cfg_t *encp; in sfc_attach() local
791 encp = efx_nic_cfg_get(sa->nic); in sfc_attach()
798 encp->enc_tunnel_encapsulations_supported; in sfc_attach()
802 encp->enc_tso_v3_enabled; in sfc_attach()
[all …]
H A Dsfc_tx.c43 if (!encp->enc_hw_tx_insert_vlan_enabled) in sfc_tx_get_offload_mask()
46 if (!encp->enc_tunnel_encapsulations_supported) in sfc_tx_get_offload_mask()
190 encp->enc_tx_tso_tcp_header_offset_limit; in sfc_tx_qinit()
192 RTE_MIN(encp->enc_tx_tso_max_header_ndescs, in sfc_tx_qinit()
195 RTE_MIN(encp->enc_tx_tso_max_header_length, in sfc_tx_qinit()
198 RTE_MIN(encp->enc_tx_tso_max_payload_ndescs, in sfc_tx_qinit()
343 if (encp->enc_tx_dma_desc_boundary != 0) { in sfc_tx_configure()
606 if (!encp->enc_fw_assisted_tso_v2_enabled && in sfc_tx_start()
607 !encp->enc_tso_v3_enabled) { in sfc_tx_start()
615 !encp->enc_tso_v3_enabled) { in sfc_tx_start()
[all …]
H A Dsfc_rx.c904 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_rx_get_offload_mask() local
907 if (encp->enc_tunnel_encapsulations_supported == 0) in sfc_rx_get_offload_mask()
979 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_rx_mb_pool_buf_size() local
1064 const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic); in sfc_rx_qinit() local
1110 encp->enc_rx_prefix_size, in sfc_rx_qinit()
1112 encp->enc_rx_scatter_max, in sfc_rx_qinit()
1118 encp->enc_rx_prefix_size); in sfc_rx_qinit()
1191 info.batch_max = encp->enc_rx_batch_max; in sfc_rx_qinit()
1192 info.prefix_size = encp->enc_rx_prefix_size; in sfc_rx_qinit()
1201 info.vi_window_shift = encp->enc_vi_window_shift; in sfc_rx_qinit()
[all …]

12