| /f-stack/dpdk/config/x86/ |
| H A D | meson.build | 15 message('SSE 4.2 not enabled by default, explicitly enabling')
19 base_flags = ['SSE', 'SSE2', 'SSE3','SSSE3', 'SSE4_1', 'SSE4_2']
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| /f-stack/freebsd/contrib/openzfs/lib/libspl/include/sys/ |
| H A D | simd.h | 59 SSE = 0, enumerator
111 [SSE] = {1U, 0U, 1U << 25, EDX },
184 CPUID_FEATURE_CHECK(sse, SSE);
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| /f-stack/dpdk/doc/guides/compressdevs/features/ |
| H A D | isal.ini | 7 CPU SSE = Y
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| H A D | default.ini | 10 CPU SSE =
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| /f-stack/dpdk/doc/guides/cryptodevs/features/ |
| H A D | aesni_gcm.ini | 10 CPU SSE = Y
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| H A D | aesni_mb.ini | 10 CPU SSE = Y
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| H A D | default.ini | 14 CPU SSE =
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| /f-stack/freebsd/contrib/openzfs/config/ |
| H A D | toolchain-simd.m4 | 35 AC_MSG_CHECKING([whether host toolchain supports SSE])
43 AC_DEFINE([HAVE_SSE], 1, [Define if host toolchain supports SSE])
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| H A D | host-cpu-c-abi.m4 | 42 dnl MMX, SSE, SSE2, 3DNow! etc.) are not frequently used. If your
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| /f-stack/dpdk/lib/librte_eal/x86/ |
| H A D | rte_cpuflags.c | 84 FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25)
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| /f-stack/dpdk/doc/guides/nics/ |
| H A D | ixgbe.rst | 11 It improves load/store bandwidth efficiency of L1 data cache by using a wider SSE/AVX register 1 (1…
17 1. To date, only an SSE version of IX GBE vPMD is available.
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| H A D | fm10k.rst | 30 SSE/AVX ''register (1)''.
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| H A D | ice.rst | 213 If it's supported, AVX2 paths will be chosen. If not, SSE is chosen.
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| H A D | bnxt.rst | 859 The BNXT PMD supports the vector processing using SSE (Streaming SIMD
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| /f-stack/dpdk/examples/l3fwd/ |
| H A D | l3fwd_em.c | 243 #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
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| /f-stack/dpdk/doc/guides/howto/ |
| H A D | debug_troubleshoot.rst | 277 feature_flags AVX|SSE|NEON using ``rte_cryptodev_info_get``.
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| /f-stack/dpdk/doc/guides/prog_guide/ |
| H A D | packet_classif_access_ctrl.rst | 373 …SIFY_SSE**: vector implementation, can process up to 8 flows in parallel. Requires SSE 4.1 support.
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| H A D | qos_framework.rst | 1380 * Fixed-point evaluation using a small look-up table (512B) and 16 SSE multiplications
1381 (SSE optimized version of the approach used in the FreeBSD* ALTQ RED implementation)
1405 …| SSE method with small (512B) look-up table | 114% …
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| H A D | cryptodev_lib.rst | 188 * SSE accelerated SIMD vector operations
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| /f-stack/dpdk/doc/guides/rel_notes/ |
| H A D | release_18_02.rst | 123 * SSE vectorized Rx/Tx burst
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| H A D | release_19_08.rst | 91 * Added support for SSE vector mode.
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| H A D | release_19_05.rst | 186 * Added support of SSE and AVX2 instructions in Rx and Tx paths.
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| /f-stack/freebsd/i386/conf/ |
| H A D | NOTES | 94 # CPU_ATHLON_SSE_HACK tries to enable SSE instructions when the BIOS has
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