| /f-stack/dpdk/drivers/net/bnxt/ |
| H A D | bnxt_ring.c | 118 stats_len = RTE_ALIGN(stats_len, 128); in bnxt_alloc_rings() 122 cp_vmem_len = RTE_ALIGN(cp_vmem_len, 128); in bnxt_alloc_rings() 126 nq_vmem_len = RTE_ALIGN(nq_vmem_len, 128); in bnxt_alloc_rings() 134 tx_vmem_len = RTE_ALIGN(tx_vmem_len, 128); in bnxt_alloc_rings() 140 rx_vmem_len = RTE_ALIGN(rx_vmem_len, 128); in bnxt_alloc_rings() 150 cp_ring_start = RTE_ALIGN(cp_ring_start, 4096); in bnxt_alloc_rings() 154 cp_ring_len = RTE_ALIGN(cp_ring_len, 128); in bnxt_alloc_rings() 156 nq_ring_start = RTE_ALIGN(nq_ring_start, 4096); in bnxt_alloc_rings() 165 tx_ring_len = RTE_ALIGN(tx_ring_len, 4096); in bnxt_alloc_rings() 172 rx_ring_len = RTE_ALIGN(rx_ring_len, 4096); in bnxt_alloc_rings() [all …]
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| /f-stack/dpdk/drivers/crypto/octeontx/ |
| H A D | otx_cryptodev_hw_access.c | 535 len = chunks * RTE_ALIGN(sizeof(struct command_chunk), 8); in otx_cpt_get_resource() 541 len = RTE_ALIGN(len, pg_sz); in otx_cpt_get_resource() 544 len += chunks * RTE_ALIGN(chunk_size, 128); in otx_cpt_get_resource() 547 len = RTE_ALIGN(len, pg_sz); in otx_cpt_get_resource() 584 mem += RTE_ALIGN(used_len, pg_sz) - used_len; in otx_cpt_get_resource() 585 len -= RTE_ALIGN(used_len, pg_sz) - used_len; in otx_cpt_get_resource() 586 dma_addr += RTE_ALIGN(used_len, pg_sz) - used_len; in otx_cpt_get_resource() 600 csize = RTE_ALIGN(chunk_size, 128); in otx_cpt_get_resource()
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| /f-stack/dpdk/lib/librte_graph/ |
| H A D | graph_populate.c | 28 sz = RTE_ALIGN(sz, val); in graph_fp_mem_calc_size() 34 sz = RTE_ALIGN(sz, RTE_CACHE_LINE_SIZE); in graph_fp_mem_calc_size() 38 sz = RTE_ALIGN(sz, RTE_CACHE_LINE_SIZE); in graph_fp_mem_calc_size() 99 off = RTE_ALIGN(off, RTE_CACHE_LINE_SIZE); in graph_nodes_populate()
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| /f-stack/dpdk/drivers/net/mlx5/ |
| H A D | mlx5_rxtx_vec.h | 45 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16)); 66 RTE_ALIGN(offsetof(struct mlx5_cqe, sop_drop_qpn), 8));
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| H A D | mlx5_txpp.c | 254 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_txpp_create_rearm_queue() 303 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_txpp_create_rearm_queue() 376 wqe_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE + in mlx5_txpp_fill_wqe_clock_queue() 391 wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE); in mlx5_txpp_fill_wqe_clock_queue() 492 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_txpp_create_clock_queue() 535 wq->sq_size = RTE_ALIGN(MLX5_TXPP_TEST_PKT_SIZE + in mlx5_txpp_create_clock_queue() 547 umem_dbrec = RTE_ALIGN(umem_size, MLX5_DBR_SIZE); in mlx5_txpp_create_clock_queue()
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| H A D | mlx5_mr.c | 65 RTE_ALIGN((uintptr_t)addr, msl->page_sz)); in mlx5_mr_mem_event_free_cb() 66 MLX5_ASSERT(len == RTE_ALIGN(len, msl->page_sz)); in mlx5_mr_mem_event_free_cb()
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| H A D | mlx5_txq.c | 840 temp = RTE_ALIGN(temp, MLX5_WSEG_SIZE) + in txq_set_params() 875 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE); in txq_set_params() 938 temp = RTE_ALIGN(temp, MLX5_WQE_SIZE); in txq_set_params()
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| /f-stack/dpdk/drivers/common/octeontx2/ |
| H A D | otx2_mbox.c | 32 return RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); in msgs_offset() 163 size = RTE_ALIGN(size, MBOX_MSG_ALIGN); in otx2_mbox_alloc_msg_rsp() 164 size_rsp = RTE_ALIGN(size_rsp, MBOX_MSG_ALIGN); in otx2_mbox_alloc_msg_rsp() 244 RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); in otx2_mbox_get_rsp() 305 RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); in otx2_mbox_get_rsp_tmo()
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| H A D | otx2_dev.c | 92 RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); in pf_af_sync_msg() 147 RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); in af_pf_wait_msg() 153 size = RTE_ALIGN(size, MBOX_MSG_ALIGN); in af_pf_wait_msg() 187 offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); in vf_pf_process_msgs() 214 size = RTE_ALIGN(size, MBOX_MSG_ALIGN); in vf_pf_process_msgs() 261 offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); in vf_pf_process_up_msgs() 363 offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); in otx2_process_msgs() 406 size = RTE_ALIGN(otx2_mbox_id2size(msg->hdr.id), MBOX_MSG_ALIGN); in pf_vf_mbox_send_up_msg() 553 offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); in otx2_process_msgs_up()
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| /f-stack/dpdk/drivers/net/fm10k/ |
| H A D | fm10k.h | 229 ((uint64_t) RTE_ALIGN(((mb)->buf_iova + RTE_PKTMBUF_HEADROOM),\ 302 if (RTE_ALIGN(addr, FM10K_RX_DATABUF_ALIGN) == addr) in fm10k_addr_alignment_valid() 306 if (RTE_ALIGN(addr, 8) == addr) { in fm10k_addr_alignment_valid()
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| /f-stack/dpdk/drivers/net/szedata2/ |
| H A D | rte_eth_szedata2.h | 35 #define RTE_SZE2_ALIGN8(what) RTE_ALIGN(what, 8)
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| /f-stack/dpdk/drivers/net/sfc/ |
| H A D | sfc_ef10.h | 108 SFC_ASSERT(RTE_ALIGN(added, SFC_EF10_RX_WPTR_ALIGN) == added); in sfc_ef10_rx_qpush()
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| /f-stack/dpdk/drivers/regex/octeontx2/ |
| H A D | otx2_regexdev.c | 96 len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8); in ree_qp_create() 99 len = RTE_ALIGN(len, pg_sz); in ree_qp_create() 105 len = RTE_ALIGN(len, pg_sz); in ree_qp_create() 129 used_len = iq_len * RTE_ALIGN(sizeof(struct otx2_ree_rid), 8); in ree_qp_create() 130 used_len = RTE_ALIGN(used_len, pg_sz); in ree_qp_create()
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| /f-stack/dpdk/lib/librte_acl/ |
| H A D | acl_gen.c | 439 indices->match_start = RTE_ALIGN(indices->match_start, in acl_calc_counts_indices() 467 total_size = RTE_ALIGN(data_index_sz, RTE_CACHE_LINE_SIZE) + in rte_acl_gen() 492 RTE_ALIGN(data_index_sz, RTE_CACHE_LINE_SIZE)); in rte_acl_gen()
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| /f-stack/dpdk/lib/librte_mbuf/ |
| H A D | rte_mbuf.c | 90 RTE_ASSERT(RTE_ALIGN(priv_size, RTE_MBUF_PRIV_ALIGN) == priv_size); in rte_pktmbuf_init() 181 RTE_ASSERT(RTE_ALIGN(priv_size, RTE_MBUF_PRIV_ALIGN) == priv_size); in __rte_pktmbuf_init_extmem() 235 if (RTE_ALIGN(priv_size, RTE_MBUF_PRIV_ALIGN) != priv_size) { in rte_pktmbuf_pool_create_by_ops() 301 if (RTE_ALIGN(priv_size, RTE_MBUF_PRIV_ALIGN) != priv_size) { in rte_pktmbuf_pool_create_extbuf()
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| /f-stack/dpdk/drivers/net/ionic/ |
| H A D | ionic_lif.c | 604 total_size = RTE_ALIGN(q_size, PAGE_SIZE) + in ionic_qcq_alloc() 605 RTE_ALIGN(cq_size, PAGE_SIZE); in ionic_qcq_alloc() 614 total_size += RTE_ALIGN(sg_size, PAGE_SIZE); in ionic_qcq_alloc() 677 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE); in ionic_qcq_alloc() 678 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE); in ionic_qcq_alloc() 681 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size, in ionic_qcq_alloc() 683 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE); in ionic_qcq_alloc() 880 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE); in ionic_lif_alloc()
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| /f-stack/dpdk/drivers/bus/vmbus/ |
| H A D | vmbus_channel.c | 112 pad_pktlen = RTE_ALIGN(pktlen, sizeof(uint64_t)); in rte_vmbus_chan_send() 156 pad_pktlen = RTE_ALIGN(pktlen, sizeof(uint64_t)); in rte_vmbus_chan_send_sglist()
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| /f-stack/dpdk/lib/librte_ethdev/ |
| H A D | rte_eth_ctrl.h | 434 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
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| /f-stack/dpdk/drivers/net/hinic/base/ |
| H A D | hinic_compat.h | 79 #define ALIGN(x, a) RTE_ALIGN(x, a)
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| /f-stack/dpdk/drivers/crypto/octeontx2/ |
| H A D | otx2_cryptodev_mbox.c | 175 RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); in otx2_cpt_af_reg_read()
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| /f-stack/dpdk/drivers/net/atlantic/hw_atl/ |
| H A D | hw_atl_utils_fw2x.c | 720 RTE_ALIGN(sizeof(*req) / sizeof(u32), sizeof(u32))); in aq_fw2x_send_macsec_request() 742 RTE_ALIGN(sizeof(*response) / sizeof(u32), sizeof(u32))); in aq_fw2x_send_macsec_request()
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| /f-stack/dpdk/drivers/net/mlx4/ |
| H A D | mlx4_rxtx.c | 427 tinfo->wqe_tso_seg_size = RTE_ALIGN(sizeof(struct mlx4_wqe_lso_seg) + in mlx4_tx_burst_tso_get_params() 434 RTE_ALIGN((uint32_t)(tinfo->fence_size << MLX4_SEG_SHIFT), in mlx4_tx_burst_tso_get_params() 753 wqe_size = RTE_ALIGN((uint32_t)(ctrl->fence_size << MLX4_SEG_SHIFT), in mlx4_tx_burst_segs()
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| /f-stack/dpdk/drivers/mempool/octeontx2/ |
| H A D | otx2_mempool_ops.c | 382 RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); in npa_lf_aura_pool_init() 471 RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); in npa_lf_aura_pool_fini()
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| /f-stack/dpdk/lib/librte_table/ |
| H A D | rte_table_lpm_ipv6.c | 88 entry_size = RTE_ALIGN(entry_size, sizeof(uint64_t)); in rte_table_lpm_ipv6_create()
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| /f-stack/dpdk/drivers/net/netvsc/ |
| H A D | hn_rxtx.c | 99 #define HN_RNDIS_PKT_ALIGNED RTE_ALIGN(HN_RNDIS_PKT_LEN, RTE_CACHE_LINE_SIZE) 103 RTE_ALIGN(RTE_ETHER_MIN_LEN + HN_RNDIS_PKT_LEN, align) 1242 padding = RTE_ALIGN(olen, txq->agg_align) - olen; in hn_try_txagg() 1521 RTE_ALIGN(pkt_size, txq->agg_align) > txq->agg_szleft) { in hn_xmit_pkts()
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