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/dpdk/doc/guides/sample_app_ug/
H A Dvmdq_forwarding.rst33 ./<build_dir>/examples/dpdk-vmdq [EAL options] -- -p PORTMASK --nb-pools NP --enable-rss
50 The application is located in the ``vmdq`` sub-directory.
59 user@target:~$ ./<build_dir>/examples/dpdk-vmdq -l 0-3 -n 4 -- -p 0x3 --nb-pools 16
82 .. literalinclude:: ../../../examples/vmdq/main.c
94 .. literalinclude:: ../../../examples/vmdq/main.c
99 .. literalinclude:: ../../../examples/vmdq/main.c
104 .. literalinclude:: ../../../examples/vmdq/main.c
H A Dvmdq_dcb_forwarding.rst100 :start-after: Empty vmdq+dcb configuration structure. Filled in programmatically. 8<
101 :end-before: >8 End of empty vmdq+dcb configuration structure.
/dpdk/drivers/net/ngbe/base/
H A Dngbe_hw.h39 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
59 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq);
60 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq);
H A Dngbe_type.h242 u32 *vmdq);
292 s32 (*set_rar)(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
295 s32 (*set_vmdq)(struct ngbe_hw *hw, u32 rar, u32 vmdq);
296 s32 (*clear_vmdq)(struct ngbe_hw *hw, u32 rar, u32 vmdq);
H A Dngbe_hw.c463 s32 ngbe_set_rar(struct ngbe_hw *hw, u32 index, u8 *addr, u32 vmdq, in ngbe_set_rar() argument
476 hw->mac.set_vmdq(hw, index, vmdq); in ngbe_set_rar()
699 u32 vmdq; in ngbe_update_mc_addr_list() local
717 ngbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); in ngbe_update_mc_addr_list()
1220 s32 ngbe_clear_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq) in ngbe_clear_vmdq() argument
1240 mpsar &= ~(1 << vmdq); in ngbe_clear_vmdq()
1256 s32 ngbe_set_vmdq(struct ngbe_hw *hw, u32 rar, u32 vmdq) in ngbe_set_vmdq() argument
1270 mpsar |= 1 << vmdq; in ngbe_set_vmdq()
/dpdk/drivers/net/ixgbe/base/
H A Dixgbe_common.h68 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
102 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
103 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);
104 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
105 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
H A Dixgbe_api.h81 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
82 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
85 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
86 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);
87 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
95 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);
H A Dixgbe_api.c893 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) in ixgbe_insert_mac_addr() argument
896 (hw, addr, vmdq), in ixgbe_insert_mac_addr()
910 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, in ixgbe_set_rar() argument
913 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, in ixgbe_set_rar()
936 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_set_vmdq() argument
938 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), in ixgbe_set_vmdq()
948 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) in ixgbe_set_vmdq_san_mac() argument
951 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); in ixgbe_set_vmdq_san_mac()
960 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_clear_vmdq() argument
962 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), in ixgbe_clear_vmdq()
H A Dixgbe_common.c2552 u32 vmdq; in ixgbe_update_uc_addr_list_generic() local
2575 ixgbe_add_uc_addr(hw, addr, vmdq); in ixgbe_update_uc_addr_list_generic()
2692 u32 vmdq; in ixgbe_update_mc_addr_list_generic() local
3720 ixgbe_set_vmdq(hw, rar, vmdq); in ixgbe_insert_mac_addr_generic()
3781 } else if (vmdq < 32) { in ixgbe_clear_vmdq_generic()
3782 mpsar_lo &= ~(1 << vmdq); in ixgbe_clear_vmdq_generic()
3785 mpsar_hi &= ~(1 << (vmdq - 32)); in ixgbe_clear_vmdq_generic()
3817 if (vmdq < 32) { in ixgbe_set_vmdq_generic()
3819 mpsar |= 1 << vmdq; in ixgbe_set_vmdq_generic()
3823 mpsar |= 1 << (vmdq - 32); in ixgbe_set_vmdq_generic()
[all …]
H A Dixgbe_vf.c315 s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, in ixgbe_set_rar_vf() argument
321 UNREFERENCED_3PARAMETER(vmdq, enable_addr, index); in ixgbe_set_rar_vf()
359 u32 vmdq; in ixgbe_update_mc_addr_list_vf() local
381 vector = ixgbe_mta_vector(hw, next(hw, &mc_addr_list, &vmdq)); in ixgbe_update_mc_addr_list_vf()
H A Dixgbe_82598.h12 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
H A Dixgbe_82598.c34 STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
916 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_set_vmdq_82598() argument
931 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK); in ixgbe_set_vmdq_82598()
942 STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_clear_vmdq_82598() argument
947 UNREFERENCED_1PARAMETER(vmdq); in ixgbe_clear_vmdq_82598()
H A Dixgbe_vf.h102 s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
/dpdk/drivers/net/txgbe/base/
H A Dtxgbe_hw.h23 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
47 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq);
48 s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq);
H A Dtxgbe_vf.c269 s32 txgbe_set_rar_vf(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, in txgbe_set_rar_vf() argument
275 UNREFERENCED_PARAMETER(vmdq, enable_addr, index); in txgbe_set_rar_vf()
313 u32 vmdq; in txgbe_update_mc_addr_list_vf() local
333 vector = txgbe_mta_vector(hw, next(hw, &mc_addr_list, &vmdq)); in txgbe_update_mc_addr_list_vf()
H A Dtxgbe_hw.c588 hw->mac.set_vmdq(hw, index, vmdq); in txgbe_set_rar()
815 u32 vmdq; in txgbe_update_mc_addr_list() local
833 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); in txgbe_update_mc_addr_list()
1483 if (vmdq == BIT_MASK32) { in txgbe_clear_vmdq()
1492 } else if (vmdq < 32) { in txgbe_clear_vmdq()
1493 mpsar_lo &= ~(1 << vmdq); in txgbe_clear_vmdq()
1496 mpsar_hi &= ~(1 << (vmdq - 32)); in txgbe_clear_vmdq()
1514 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq) in txgbe_set_vmdq() argument
1526 if (vmdq < 32) { in txgbe_set_vmdq()
1528 mpsar |= 1 << vmdq; in txgbe_set_vmdq()
[all …]
H A Dtxgbe_vf.h48 s32 txgbe_set_rar_vf(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
H A Dtxgbe_type.h464 u32 *vmdq);
561 s32 (*set_rar)(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
565 s32 (*set_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
566 s32 (*clear_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
/dpdk/drivers/net/mlx5/
H A Dmlx5_mac.c124 uint32_t index, uint32_t vmdq __rte_unused) in mlx5_mac_addr_add()
/dpdk/examples/
H A Dmeson.build62 'vmdq',
/dpdk/drivers/net/mlx4/
H A Dmlx4.h218 uint32_t index, uint32_t vmdq);
H A Dmlx4_ethdev.c486 uint32_t index, uint32_t vmdq) in mlx4_mac_addr_add() argument
492 (void)vmdq; in mlx4_mac_addr_add()
/dpdk/drivers/net/i40e/
H A Di40e_ethdev.c1943 pf->vmdq[i].vsi = NULL; in i40e_dev_configure()
1945 rte_free(pf->vmdq); in i40e_dev_configure()
1946 pf->vmdq = NULL; in i40e_dev_configure()
2615 pf->vmdq[i].vsi = NULL; in i40e_dev_close()
2617 rte_free(pf->vmdq); in i40e_dev_close()
2618 pf->vmdq = NULL; in i40e_dev_close()
6471 if (pf->vmdq != NULL) { in i40e_vmdq_setup()
6479 if (pf->vmdq == NULL) { in i40e_vmdq_setup()
6531 rte_free(pf->vmdq); in i40e_vmdq_setup()
6532 pf->vmdq = NULL; in i40e_vmdq_setup()
[all …]
/dpdk/drivers/net/failsafe/
H A Dfailsafe_ops.c1389 uint32_t vmdq) in fs_mac_addr_add() argument
1398 ret = rte_eth_dev_mac_addr_add(PORT_ID(sdev), mac_addr, vmdq); in fs_mac_addr_add()
1410 PRIV(dev)->mac_addr_pool[index] = vmdq; in fs_mac_addr_add()
/dpdk/drivers/net/mvneta/
H A Dmvneta_ethdev.c638 uint32_t index, uint32_t vmdq __rte_unused) in mvneta_mac_addr_add()

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