Searched refs:rte_vect_get_max_simd_bitwidth (Results 1 – 24 of 24) sorted by relevance
117 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) in acl_check_alg_arm()121 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) in acl_check_alg_arm()139 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) in acl_check_alg_ppc()169 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512) in acl_check_alg_x86()178 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) in acl_check_alg_x86()187 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) in acl_check_alg_x86()196 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) in acl_check_alg_x86()
254 max_simd_bitwidth = rte_vect_get_max_simd_bitwidth(); in rte_crc16_ccitt_default_handler()274 max_simd_bitwidth = rte_vect_get_max_simd_bitwidth(); in rte_crc32_eth_default_handler()296 max_simd_bitwidth = rte_vect_get_max_simd_bitwidth(); in rte_net_crc_set_alg()
216 uint16_t rte_vect_get_max_simd_bitwidth(void);
213 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) in ip4_lookup_node_init()
390 rte_vect_get_max_simd_bitwidth;
648 && rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) in rte_efd_create()659 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) in rte_efd_create()
2913 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { in iavf_set_rx_function()2916 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) in iavf_set_rx_function()2922 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512) in iavf_set_rx_function()3066 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { in iavf_set_tx_function()3072 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) in iavf_set_tx_function()3078 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512) in iavf_set_tx_function()
3249 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { in ice_set_rx_function()3259 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 && in ice_set_rx_function()3271 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) in ice_set_rx_function()3509 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { in ice_set_tx_function()3512 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 && in ice_set_tx_function()3524 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) in ice_set_tx_function()
575 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) in mlx5_check_vec_rx_support()
67 (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_512)) in get_vector_fn()
50 (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_512)) in get_vector_fn()
118 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) in rte_member_create_ht()
821 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) { in enic_use_vector_rx_handler()
764 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) in rte_distributor_create()
3205 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 && in get_avx_supported()3216 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && in get_avx_supported()3275 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { in i40e_set_rx_function()3467 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { in i40e_set_tx_function()
99 (rte_vect_get_max_simd_bitwidth() >= in rte_thash_gfni_supported()
2674 rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_512)) { in virtio_dev_configure()2685 rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)) { in virtio_dev_configure()2739 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) { in virtio_dev_configure()
2945 rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) { in fm10k_set_tx_function()2965 rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) in fm10k_set_tx_function()3000 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { in fm10k_set_rx_function()
601 rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) in axgbe_dev_tx_queue_setup()
1262 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && in bnxt_receive_function()1271 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { in bnxt_receive_function()1315 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && in bnxt_transmit_function()1323 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { in bnxt_transmit_function()
2125 rte_vect_get_max_simd_bitwidth(void) in rte_vect_get_max_simd_bitwidth() function
593 'rte_vect_get_max_simd_bitwidth()' function.606 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512)608 else if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
2457 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128 && in ixgbe_dev_tx_done_cleanup()2557 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128 && in ixgbe_set_tx_function()4791 rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) { in ixgbe_set_rx_function()
2812 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) in hns3_get_default_vec_support()2824 if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) in hns3_get_sve_support()